High-speed parallel interfaces now operate at speeds in excess of 1600 MTps, with timing margins well under 100 ps. At these speeds, detailed timing/SI analysis is needed to ensure design setup/hold margins are both sufficient and properly centered. Power integrity analysis gets added to this mix, predicting how switching events will affect the interface's timing budget. Device timing is measured and guaranteed under specific conditions that drive the details of how signal/power integrity simulations must be performed and simulation results measured. Understanding these details is essential to combined timing/SI/PI analysis that correctly predicts the interface operating margin.