Embedding capacitive layers inside the PCB have demonstrated the ability to reduce the number of SMT chip-decoupling capacitors on the PCB surface, as well as greatly improve the performance of the power distribution system. Many systems today utilize this technology, but most public information is limited to data on test vehicles or emulators. This paper utilizes simulated as well as measured product data to compare the performance of the standard design to one using various types of Buried Capacitance^TM layers with a reduced number of SMT decoupling capacitors. A methodology is provided that can be utilized for other designs.