SSN-induced timing variations limit achievable data rates of modern nano-technology devices. We developed measurement methods to separate various sources of FPGA signal timing pull-in/push-out due to simultaneously switching I/Os, with both synchronous and asynchronous cases considered. We revealed three main mechanisms of timing variations: crosstalk, delta-I noise, and PDN resonance. The obtained results can be used as a design guideline to reduce timing variations due to SSN.