4-TP2
Simulations and Characterizations for GHz On-Chip Power Delivery Network (PDN)
Tuesday, February 5 | 2:50 pm – 3:30 pm
Vishram S. Pandit, Senior Engineer, Intel
Woong Hwan Ryu, Senior Staff Engineer, Intel
Kirupa Pushparaj, Intel Corporation
Sankalp Ramanujam, Intel Corporation
Farag Fattouh, Intel
A correlation study for on-die PDN is performed by comparing measurements and simulations. A novel test vehicle, RF silicon-to-simulation, is designed to determine the on-die PDN performance. It comprises only power and ground domains with power grid and on-die decoupling capacitor (decap). Three types of structures are implemented: power grid with on-die decap, power grid only — open, and power grid only — short. These structures are simulated with the external commercial tool RH_PG. The measurements are done using on-wafer VNA and correlated with simulations. The detailed models for the power grid and the decoupling capacitor are extracted.
Woong Hwan Ryu, Senior Staff Engineer, Intel
Kirupa Pushparaj, Intel Corporation
Sankalp Ramanujam, Intel Corporation
Farag Fattouh, Intel
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