A wide-range transceiver, 622 Mbps to 6.5 Gbps, was designed and fabricated in a 90 nm TSMC CMOS logic process. Voltage offsets in the receive path degrade the performance of the transceiver by putting a lower bound on the precision with which a data bit can be measured and cause duty cycle distortion, which, when added with ISI, reduce the overall margin of data recovery directly worsening the BER. Presented in this paper is a methodology to cancel voltage offsets in the receive path with a soft intellectual property core programmed in the PLD.