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2-WP1
How to Find if Your Checker Is Complete and Exhaustive — A Set of Guidelines Using Systemverilog and Memory Controller Example
Wednesday, February 6 | 2:00 pm – 2:40 pm

Leena Singh, Verification Architect, Rambus
Dinesh Malviya, Lead Engineer, Rambus
In any verification project, one of the most important questions before signing off is, are there any more possibilities of bugs in the design? An answer to this depends upon how extensive the checklist is and how complete and reliable the checkers implemented in the verification environment are. This paper will address with an example a strategic way to plan and implement checkers in any verification environment to ensure correctness of the functionality you are verifying. It will also address how you can relate functional coverage goals with actual checks implemented as assertions, response checkers, end-to-end checkers, or reference checks.