FPGA synthesis tools have progressed in getting "the fastest and smallest implementation" for every possible design. These tools adopt aggressive optimizations and mapping techniques to efficiently use the FPGA real estate. The size and complexity of FPGA designs has caused design verification to be used in every step of the design process.

While simulation and prototyping are still the norm for verifying design functionality, formal verification (FV) has become an invaluable tool in verifying the netlist at various stages of the design flow.

This paper focuses on the issues faced by designers when using FV flow in FPGA designs.