Despite a number of new tools that provide exhaustive CDC verification, the dramatic increase in the complexity of chips and the number of clock domains on them continues to make CDC verification painfully difficult to do. In this paper, we present a hierarchical CDC verification technology that enables CDC verification to start as early as the block level and reuses the analysis results to seamlessly continue verification on through to the top level. We will describe the methodology we developed to effectively use this technology on a communication chip design. The results and the advantages will be presented.