This paper presents a system-level methodology to handle design of complex application-specific engines, key differentiators in modern SoCs. This methodology is based on high-level synthesis: from an untimed C-based description of the algorithm, it produces an optimal hardware implementation meeting constraints of maximum throughput, memory bandwidth/porting requirements and desired parallelism/task-overlap, on the targeted ASIC technology. We demonstrate this methodology in two complex and high performance multimedia designs: (1) image signal processing pipeline comprising of sub-modules performing various image restoration/enhancement tasks consisting of inter-block streaming interfaces and (2) multi-standard (H.264,VC1,MPEG4,H.263) de-blocking and de-ringing filter with memory block-based inter-modular interfaces.