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A phase-locked loop (PLL) reset control apparatus is designed for a proper PLL power-up sequence and auto-synchronization. A very specific PLL power-up sequence during normal mode of operation as well as during reset mode is essential for PLL functionality and performance. This reset control apparatus ensures PLL components "wake up" in an orderly manner for proper operation when a user presses reset in order to resynchronize the PLL. This reset control machine takes two signals as input (user reset pulse and clock signal) and generates internal reset signals for each PLL comprising blocks.