Ping Yeung, Principal Engineer, Mentor Graphics
Chris Kwok, Mentor Graphics
Matt Berman, Mentor Graphics
Harry Stuimer, Senior Staff Engineer, Sun Microsystems
Scott Wakefield, Design Engineer, Sun Microsystems
Eugena Talvola, Senior Verification Engineer, Sun Microsystems
Catherine Ahlschlager, Formal Verification Manager, Sun Microsystems

Multiple voltage and clock domains are used extensively in processor designs to reduce power consumption. For high-performance multi-core designs, clocks in various cores and sub-systems are ratio synchronous and periodically aligned. We call this a ratio synchronous clock (RSC) scheme. It enables predictable behavior and allows dynamic voltage frequency scaling (DVFS) techniques to be efficiently deployed to meet power budget requirements. In this paper, we will summarize various RSC schemes. We will focus on the design and use of RSC schemes in the UltraSPARC T2, 8-core, 64-thread processor from Sun Microsystems. In addition, we will describe a verification methodology that makes RSC schemes reliable for high-speed processor designs.