We present a case study in using the VSIA QIP to evaluate internally developed IP. We found that using the VSI QIP rating system could be used to indicate how much engineering effort would be required to integrate a piece of IP into a new design. In this work we intergraded IP previously developed internally (5-bit ADC and DAC) into a 5-tap, 5-bit, FIR filter designed with a Cadence-based ASIC flow. We had access to the original files of ADC/DAC as well as testing results from a manufactured chip. Although the project manager was available to answer questions, the authors of the IP were not. In this environment it was found that most of the engineering effort went into integrating the ADC/DAC IP and not the design of the FIR filter. The low VSI QIP score for item 1.1.1.3 (defining interfaces) of the ADC/DAC indicated that more time would be required to integrate the IP before work on this project began, thus giving the designer and project manager a clearer picture of the time required to finish this project.