This paper discusses fundamental constraints of current packaging technology and how they affect the performance of multichannel 10 Gbps FPGAs. These FPGA packages act as interconnects between dies and system boards. While IC chips take advantage of Moore's law in dimension and cost reduction, system boards traditionally have not. From design optimization practice, we conclude that the inherent dimension mismatch among layout features that link the die to boards hampers the upper limit of bandwidth. To overcome these constraints, we propose advanced technologies such as coreless, fine-pitch packages and demonstrate extended 40 GHz bandwidth, making performance comparable to state-of-art microwave devices.