"Performance at the DUT" is the ideal specification for an ATE test fixture. Fast slew rates of multi-gigabit signals can easily be degraded by the interaction of the test fixture's PCB, socket, and DUT interfaces, making it difficult to predict the performance at the DUT. This paper presents the results of an effort to address these challenges and show results for an application running at 6.4 Gbps on an ATE system. Topics include probing techniques for characterizing the test fixture at the DUT socket interface, calibration and 3D-EM simulation methods for de-embedding the probe effects, and synthesized performance at the DUT.