10-TA3
Analyzing the Impact of Simultaneous Switching Noise on System Margin in Gigabit Single-Ended Memory Systems
Tuesday, February 5 | 10:15 am – 10:55 am
Ralf Schmitt, Senior Engineering Manager, Rambus
Joong-Ho Kim, Senior Member of Technical Staff, Rambus
Woopoung Kim, Senior Member of Technical Staff, Rambus
Dan Oh, Engineering Manager, Rambus
June Feng, Senior Member of Technical Staff, Rambus
Chuck Yuan, Signal Integrity Engineer, Rambus
Lei Luo, Rambus
John Wilson, Rambus
Simultaneous switching noise is a major performance limiter for single-ended signaling systems as data rates scale higher. This paper presents a methodology to analyze the performance of single-ended interface systems such as GDDR3 in the presence of signal and supply noise. We present a compact model for signal and supply integrity co-simulation and study the impact of supply noise and VREF noise on the system margin. A methodology to identify minimum system margin at worst-case excitation is presented, and the effectiveness of DBI noise reduction coding is investigated. Finally, the system performance for different package and motherboard implementations is compared.
Joong-Ho Kim, Senior Member of Technical Staff, Rambus
Woopoung Kim, Senior Member of Technical Staff, Rambus
Dan Oh, Engineering Manager, Rambus
June Feng, Senior Member of Technical Staff, Rambus
Chuck Yuan, Signal Integrity Engineer, Rambus
Lei Luo, Rambus
John Wilson, Rambus
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