Contact: Lisa Reyes
Phone: +1-312-559-3325
E-mail: lreyes@iec.org
Best Papers and Presentations in Semiconductor Industry Announced Today at DesignCon 2007 in Santa Clara
IEC Recognizes 2007 DesignCon Paper Award Finalists Spotlighting Outstanding Contributions to Educational Goals of DesignCon Program
CHICAGO – January 29, 2007 – The International Engineering Consortium (IEC) today announced the 2007 DesignCon Paper Award Finalists of DesignCon 2007, which takes place this week at the Santa Clara Convention Center in Santa Clara, CA.
More than 300 industry experts will speak at this year's DesignCon in more than 100 educational tutorials, plenary panels, paper presentations, and sessions.
IEC's DesignCon Program Director, Dr. Barry Sullivan commented, "We chose 26 finalists from 88 papers making up the DesignCon 2007 technical program, which is an indication of the broad range of topics presented at this year's DesignCon."
The Awards serve to acknowledge the winning authors as leading practitioners in semiconductor and electronic design. The Awards also provide incentive to authors to produce high-quality DesignCon papers and present them in a lucid and compelling manner.
Judges were selected from the DesignCon 2007 Technical Program Committee, which was comprised of ninety-six of the industry's top thought leaders.
2007 Paper Award Finalists include the following authors and papers in their respective categories:
Application-Specific Design Category
- Gordon Hands, "High Performance Image Interfaces in Low-Cost Programmable Logic"
- Olivier Despaux, "Optimizing Memory Interfaces for Specific Applications"
- Ken Umino and Peter Thoeming, "Comparison of a 1x Clock DDR Design versus a 2x Clock DDR Design"
Chip-Level Design Category
- Graham Allan and Jody Defazio, "IP Solves the Increasing Challenge of Implementing an Interface to Off-Chip DDR SDRAM"
- Larry Smith and Hong Shi, "FPGA Design for Signal and Power Integrity"
- Daniel Wu, Lawrence Williams and Minhong Mi, "RFID Radio Circuit Design in CMOS"
- Alex Rubin, Uwe Fassnacht, Frank Borkam and Paul Campbell, "Practical Clock Skew Scheduling on a High Performance Processor"
- Mark Bailey, Greg Edlund, Bob Morse and Ankur Patel, "Packaging a Supercomputer in a PCI Express Form Factor"
Functional Verification Category
- Divya Vijayaraghavan, "Serial Protocol Compliance of an FPGA-Integrated Mixed-Signal Transceiver"
- Alfonso Íñiguez, "Dissecting Multi-Million Gate Design Bugs"
- Harry Foster and Ping Yeung, "Planning Formal Verification Closure"
Board-Level Design Category
- Abdemanaf Tambawala, Ege Engin, Madhavan Swaminathan, Pranabes Pramanik, Kazuhiro Yamazaki and John Andresakis, "Compact Electromagnetic Bandgap Structures for Power Plane Isolation Using High-K Dielectrics"
- Pat Zabinski, Ben Buhrow, Barry Gilbert and Erik Daniel, "Applications of Optimization Routines in Signal Integrity Analysis"
- Heidi Barnes, Antonio Ciccomancini, Mike Resso and Ming Tsai, "Differential PCB Structures using Measured TRL Calibration and Simulated Structure De-Embedding"
Interconnect Design Category
- Jason R. Miller, Gustavo Blando and Istvan Novak, "Crosstalk Due to Periodic Plane Cutouts"
- Andrew J. Kim and Michael Vrazel, "Improving the Reach-Gauge Tradeoff in Copper Cable Interconnects"
- Jan De Geest, Dana Bergey, John Lynch Dennis Miller and Stefaan Sercu, "Improving System Performance by Reducing System Impedance to 85 Ohms"
System-Level Design Category
- Martin Mücke, Marcus Müller and Joachim Moll, "Precision Digital Noise Source"
- Mike Li, "Simultaneous Jitter Analysis in Time, Frequency, and Statistical Domains and Their Interrelationships"
- Johnnie Hancock, "Real-time Sampling Technique Affects Accuracy of High-speed Digital Measurements"
- Jihong Ren, Haechang Lee, Brian Leibowitz, Qi Lin, Ruwan Ratnayake, Kyle Kelly, Vladimir Stojanovic, Dan
- Oh, Jared Zerbe, and Nhat Nguyen, "Performance Comparison of Edge-Based Equalization and Data-Based Equalization for Transmitter and Receiver"
Power and Test Category
- Ralf Schmitt, Hai Lan, Chris Madden and Chuck Yuan, "Analysis of Supply Noise Induced Jitter in Gigabit I/O Interfaces"
- Om P. Mandhana, Hector Sanchez, Joshua Seigel and Jonathan Burnett, "Study of Simultaneous Switching Noise Reduction for Microprocessor Packages by Application of High-K MIM Decoupling Capacitors"
- James L. Drewniak, Bruce Archambeault, James Knighten, Giuseppe Selli, Jun Fan, Matteo Cocchini, Samuel Connor and Liang Xue, "Comparing Time-Domain and Frequency Domain Techniques for Investigation on Charge Delivery and Power-Bus Noise for High-Speed Printed Circuit Boards"
- Masahiro Ishida, Takahiro J. Yamaguchi and Mani Soma, "A Method for Testing Jitter Tolerance of SerDes Receivers Using Random Jitter"
- Brett Grossman, Tom Ruttan and Evan Fledell, "Architectural Considerations for Multiport Vector Network Analyzers"
The IEC will also present the 2006 Paper Awards to last year's winners at DesignCon this Wednesday, January 31 at 10:30 a.m. before the Wednesday Plenary Panel. Winners were chosen on both the merits of the written document and on the quality of their presentation at DesignCon 2006.
Industry professionals can gain access to technical sessions with a conference pass available at DesignCon 2007 in the Santa Clara Convention Center. Complimentary access is available for the Paper Awards presentation, plenary panel, keynote addresses, all major sessions and the exhibition floor by printing out an Exhibits Only Pass at www.designcon.com/2007/.
For complete information, contact Lisa Reyes at lreyes@iec.org.
About DesignCon
DesignCon serves as the premier event for practicing engineers in the electrical design and semiconductor communities. Broadening the scope to address business as well as technical issues of the industry, DesignCon 2006 hosted 125 exhibiting companies and drew more than 5,000 industry professionals to register. This year's DesignCon will host more than 300 industry experts to speak in more than 100 educational tutorials, plenary panels, paper presentations, and sessions at DesignCon. Complementing the conference, more than 125 exhibitors are expected to take the floor exhibiting the latest technological developments. Visit www.designcon.com/2007.
About the IEC
A nonprofit organization, the IEC is dedicated to catalyzing technology and business progress worldwide in a range of high-technology industries and their university communities. Since 1944, the IEC has provided high-quality educational opportunities for industry professionals, academics, and students.
In conjunction with industry-leading companies, the IEC has developed an extensive, free, on-line educational program. The IEC conducts industry-university programs that have a substantial impact on curricula. It also conducts research and develops publications, conferences, and technological exhibits that address major opportunities and challenges of the information age.
More than 70 leading high-technology universities are IEC affiliates, and the IEC handles the affairs of the Electrical and Computer Engineering Department Heads Association and Eta Kappa Nu, the honor society for electrical and computer engineers. The IEC also manages the activities of the Enterprise Communications Consortium. Visit www.iec.org.
