Booth #928

San Jose, CA USA phone: 408 918 7918 fax: 408 298 0144 www.chipeda.com

ChipEDA is a provider of EDA tools and services to IC design companies. By using our Chipmason^TM tool set and our proven technology, design teams are able to exploit the performance of submicron geometries without incurring the usual productivity and schedule penalties.

Our partition and Re-Use methodology enable multi-million instance designs to be tackled efficiently augmenting design teams' existing EDA tools resulting in significant cost reduction and shorter time to market. For more info: www.chipeda.com

ChipMason^TM is an EDA tool set that is used by our customers for rapid silicon prototyping and detailed floor planning. A designer can go from logic design view, be it behavioral specification or detailed gate level netlist, to a detailed floorplan with IO pads, power grid and quickly find and solve congestion areas as well as critical timing paths. It enables a top down hierarchical design methodology. It can partition very large designs allowing the user to create consistent and accurate layout and timing abstracts and detailed views. A key element of the methodology utilizing our tool set is the ability to reuse layout blocks, within the same chip or in different chips.

FloorMason^TM is part of ChipMason tool set. It is a complete floor planning and silicon prototyping tool, its main features are: hierarchical, top down, design partitioning; physical blocks shape generation; relative and absolute block placement; automated pin allocation; allows controlled adjustments to block placement, pin allocation and timing budgets; automated time budgeting; detailed power grid generation including power islands and multi voltage supply; budgeting constraints and abstract generation for every layout block; repeater insertion into the layout blocks; detailed placement of PADS and Near-Pad-Logic; hierarchical scan chain insertion - bottom up approach; scan chain insertion/stitching; can handle very large chips (>20M instances); and re-use methodology at the layout level.

dpMason^TM is part of ChipMason tool set. It is used to generate dense data path elements found in CPU and DSP design. It includes a small register file and memory generator. Its main features are: based on standard cells; very compact layout, layout density up to 98%; generated outputs include verilog netlist, DEF file (cells placement), and timing and layout abstracts; fully integrated in ASIC flow; supports pipeline registers generation with balanced clock tree; can combine control blocks with data path elements; and fully integrated into FloorMason.