Booth #918

Richardson, TX USA phone: 972-437-2800 fax: 972-437-2806 www.asset-intertech.com

ASSET InterTech, Inc. develops and sells boundary-scan testability and in-system programming (ISP) products worldwide. ASSET's affordable ScanWorks® JTAG test environment allows users to quickly test circuit boards during every phase of a product's lifecycle.

ASSET's DFT Analyzer^TM validates the JTAG Design for Test attributes of a hardware design, reducing cost of test and accelerating time-to-market. BSDL Validation Service troubleshoots JTAG insertion and BSDL file errors within silicon. And ScanWorks® Intel® IBIST supports Intel's next-generation design validation and embedded test methodology.

DFT Analyzer^TM from ASSET® InterTech Inc., (www.asset-intertech.com) an international leader in boundary-scan (IEEE 1149.1/JTAG) test and in-system programming (ISP), reduces manufacturing and test costs by validating the boundary-scan design-for-test (DFT) features in a circuit board design before any prototypes are assembled. In addition, DFT Analyzer determines the extent of a design's boundary-scan test coverage and recommends changes that would increase coverage. DFT Analyzer alleviates schedule risks and reduces test and prototyping costs by alerting designers and test engineers early in the process when it is easier and much less costly to design testability into the product. Limiting or eliminating entirely the need for a board re-design saves significant costs.

ASSET InterTech (www.asset-intertech.com) offers a two-prong approach to validating the accuracy of a chip's Boundary Scan Description Language (BSDL) file. First, a device's BSDL file can be submitted to ASSET's free BSDL Validation Service (www.asset-intertech.com/bsdl_service) for syntactic and semantic checking. This site was developed by ASSET and Agilent Technologies. With sample silicon, ASSET's BSDL Silicon Validation Service verifies the accuracy of 1149.1/1149.6 BSDL files against a chip. A fixture tests power and ground, access to each I/O and the boundary scan signals of TRST, TMS, TCK, TDI and TDO, and static control of compliance-enable pins. Lastly, a test sequence is generated for the device to empirically validate that its embedded JTAG capabilities are described accurately in its BSDL file.