Booth #921

Milpitas, CA USA phone: 408-717-4911 fax: 408-904-5721 www.archpro-da.com

ArchPro has developed a comprehensive low power management verification tool suite, built upon MVSIM^TM, MVRC^TM and MVSYN^TM — tools that are uncovering fatal design issues, not found by other industry tools, in the architectural/RTL/gate level of the design cycle — saving months in product development cycles by eliminating chip respins and expensive silicon debug time. ArchPro's products are silicon proven on the most advanced power management techniques available today: voltage islands, power gating, dynamic and adaptive voltage frequency scaling, body bias, low Vdd standby, etc.

ArchPro's Multi-Voltage SIMulator (MVSIM^TM) enables verification of power managed designs at the RTL and gate level. MVSIM^TM provides a comprehensive verification solution to the multi-voltage design woes faced by the semiconductor and electronic systems industry. MVSIM^TM annotates the multi-voltage information with the designers' RTL and works with your existing functional simulator to perform a realistic multi-voltage verification. This allows a design team to comprehend the correctness of their design with respect to the multiple voltages used across several blocks at a very early stage in the design flow. MVSIM^TM can accurately simulate techniques such as, Dynamic Voltage Scaling, Adaptive Voltage Scaling, Power Gating, Retention and Body-Bias.

ArchPro's MVRC^TM enables vectorless verification and validation of power managed designs at every stage of the design flow (RTL to post-route netlist), eliminating costly repins and silicon debug time. MVRC^TM identifies missing or incorrect level shifters and isolation gates, points out bad states in the power management scheme, and detects faulty protection circuitry connections. MVRC^TM enables designers to debug the power management scheme interactively or interface with a third party tool using an API. Unlike conventional tools which allow equivalence checking only for a single VDD level, MVRC^TM enables the designer to verify and validate equivalence between various netlists for all power management states of the design.

ArchPro's MVSYN^TM enables a fully automated, scriptless multi-voltage synthesis of protection circuitry (isolation cells and level shifters) at both the RTL and gate level for power managed designs — eliminating human error, ensuring first-pass success and accelerating Time-To-Market. MVSYN^TM also seamlessly handles late-stage ECO's by comprehending the change needed and optimally updating the protection logic in the design to conform to the new power management scheme. Further, this can be done at any stage in the design — RTL through post-route, gate level netlist. MVSYN^TM also has an incremental mode that helps designers close to tapeout time, when schedule pressure is at its peak, by inserting only the protection circuitry that is required, while also preserving protection circuitry that already exists in the design.