Booth #503

San Jose, CA USA phone: 408-544-7000 Fax: 408-544-7809 www.altera.com

Altera Corporation, headquartered in San Jose, California, develops programmable solutions enabling system and semiconductor companies to rapidly and cost-effectively innovate, differentiate, and win in their markets. The Altera product portfolio includes the industry's most advanced FPGA, CPLD, and structured ASIC technologies; versatile embedded processors; intellectual property cores; a fully integrated software development tool; and off-the-shelf development kits. Learn more at www.altera.com

Altera® Stratix III FPGAs feature innovative Programmable Power Technology that dramatically lowers power while meeting high-performance requirements. Reduced power consumption is achieved by utilizing Programmable Power Technology, which maximizes performance where needed while delivering the lowest power elsewhere in the design. It enables every programmable logic array block (LAB), digital signal processing (DSP) block, and memory block to operate independently at high-speed or low-power mode. The PowerPlay feature in Quartus® II software version 6.1 automatically analyzes the design, identifying which blocks are in the critical path and will demand the highest performance, setting these to high-speed mode. All other blocks are automatically put into low-power mode.

Altera's PELE (Pre-Emphasis and Equalization Link Estimator) tool has been integrated into the Mentor Graphics® HyperLynx design platform. PELE, a new productivity and ease-of-use tool for verifying high-speed designs, allows designers to quickly and easily estimate signal integrity settings, and simulate and predict system performance. PELE takes months off the verification time when compared to verification on a laboratory test bench. Seamlessly integrated into the HyperLynx design flow, PELE has the ability to directly import the frequency-domain files from either Mentor's board layout tools or customer measured data, and to configure Mentor's ELDO analog simulator directly, substantially improving productivity and decreasing design risk.

The high-density Stratix® II GX family provides up to 20 low-power transceivers operating between 600 Mbps and 6.375 Gbps with an unprecedented 127 Gbps of aggregate serial link connectivity. The Stratix II GX FPGA transceivers' optimized signal integrity has been demonstrated for boards and backplanes using FR-4 materials at over 1.25 meters length, thus lowering OEM system costs and improving manufacturing yields. These low-power transceivers also lower cost by reducing cooling system complexity and associated equipment maintenance expenses. Customers are now using Stratix II GX FPGAs to design and manufacture multi-gigabit-interconnected systems that meet or exceed their performance and signal integrity specifications.