FPGAs are ideal for ASIC prototypes because of speed, complexity, and cost - except they lack the visibility required for debug. Likewise assertions are ideal for ASIC verification because of their visibility and controllability. This paper highlights Synplicity's TotalRecall™ technology which allows verification engineers to conveniently capture events leading up to an error and export the information to their favorite simulator for analysis. This permits verification at full hardware speed with live input while maintaining a familiar simulator interface for debug. This patented technology provides FPGA based prototypes and assertions running in hardware with a higher level of design visibility and debug than traditional methods.
Mario Larouche, Engineering Director, Synplicity
Mario Larouche is responsible for overseeing the creation of Synplicity's FPGA verification & debug solutions, including the patented TotalRecall Verification Technology. Mr. Larouche has been involved in creating EDA solutions in the synthesis, simulation and design debugging areas since 1989 and is the author, or co-author of five Synplicity patents for System Debugging.
