As serial links speeds exceed 5 Gbps, receiver eyes close and mask-based design techniques become impossible. System and silicon designers must validate an end-to-end model that includes transmitter, receiver, and channel characteristics; transmitter and receiver equalization; clock data recovery; error correction; and the effects of system level crosstalk.
Successful modeling requires a mixture of time domain, frequency domain and statistical methods. This TecPreview presents SiSoft's solution to validating 5-20 Gbps serial links, including a standards-based SERDES IP modeling strategy that allows the prediction of end-to-end link BER including the effects of system level crosstalk. SiSoft's unique approach includes the first-ever serial link EDA tool to provide integrated crosstalk analysis yielding optimum routing strategies at both the pre- and post- layout stages.
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Todd Westerhoff
Vice President, Software Products
SiSoft
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Todd has over 26 years experience in modeling and simulation, including 10 years of signal integrity experience. Before joining SiSoft, Todd managed a signal integrity group at Cisco Systems, providing advanced design support to multiple engineering teams. Todd previously held positions with Cadence, Racal-Redac, FutureNet, HHB-Systems and GenRad.
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