Ashok Kulkarni, Senior Manager, Synplicity, Inc.
Ken McElvain, Chief Technical Officer/Vice President, Synplicity, Inc.
Mario Larouche, Engineering Director, Synplicity, Inc.

Traditional debug techniques cannot be applied to complex FPGAs anymore. What is required is the ability to find errors in a design running in a live FPGA by going back in time several hundred clock cycles and recall exactly what a design's state was at that time, combined with several hundred clock cycles of inputs to that design. In this paper, we will describe a methodology that shows how to locate the bug using synthesizable SystemVerilog assertions in a running FPGA and recall the events leading up to an error and export the information to your favorite simulator for analysis.