Brian Bailey, Chief Technologist, Poseidon Design Systems
Grant Martin, Chief Scientist, Tensilica, Inc.
Andrew Piziali, Senior Product Engineer, Cadence Design Systems
With chip sizes of 250 million transistors and total system complexity rising at an ever-faster rate, electronic system level (ESL) design and verification has become a necessity rather than a technology of the future. Dataquest predicts explosive growth for the area, but in the EDA community, it never quite seems to happen. In reality it is already here and in use by many of the top design companies in the world. This tutorial will provide a comprehensive guide to the current state of the industry ranging from systems specification through partitioning, analysis, implementation, and verification.
