The role of process variation in the design of integrated circuits can no longer be ignored at any phase of the design flow. Process variation is about to be required in the design, characterization, and use of design libraries and IP, and it is no doubt going to be an expensive proposition in the time it takes to perform the measurements and characterization and drastically expand the storage required for the statistical information. This panel will explore the requirements, costs, and benefits of modeling process variation and the use of the information in today's and tomorrow's class of integrated circuit design.

Nick English Vice President, Development Silicon Integration Initiative

Mr. English is known for managing both business and technical processes that affect electronic design. He has more than 25 years of high-technology industry experience in both engineering and management roles. Mr. English has previously served as the chair and the key driver of the OpenKit Initiative in Accellera to create standards for the semiconductor industry's process design kits. Over the past 20 years, he has held senior management positions in semiconductor, EDA, and software companies.

Vinod Kariat Senior Member Cadence Design Systems

Dr. Kariat received his Ph.D. in computer engineering from Syracuse University and subsequently worked for eight years at IBM. Dr. Kariat pioneered the use of static noise analysis techniques while working at the IBM T. J. Watson Research Center. He was vice president of engineering at CadMOS Design Technology, a start-up devoted to the commercialization of static noise analysis techniques, which he co-founded in 1997. Vinod has been with Cadence in various management and senior technical positions since Cadence acquired CadMOS in 2001. He now works on advanced analysis technology development. Dr. Kariat is a senior member of the IEEE and holds six patents.

Jim McCanny Chief Executive Officer and Co-Founder Altos Design Automation

Before joining Altos, Mr. McCanny was the timing and signal integrity marketing group director at Cadence. He was the vice president of marketing and business development at CadMOS when it was acquired by Cadence in 2001. Before CadMOS, Mr. McCanny was executive vice president at Ultima Interconnect Technology (which, as Celestry, was acquired by Cadence in 2003), major account technical program account manager at EPIC Design Technology (which went public in 1994), and a member of the group technical staff at Texas Instruments. Jim holds a B.S. in math/computer science from Manchester, England, and has more than 25 years of experience in EDA.

Ayhan Mutlu Member of Technical Staff Extreme-DA

Dr. Mutlu develops methodologies and algorithms for handling process variations in the statistical timing analysis and RC extraction flows. Prior to joining Extreme-DA, he worked for Intel Corporation in Santa Clara, California, specializing in the development of design automation tools for next-generation process technologies. Dr. Mutlu is also an adjunct professor of electrical engineering at Santa Clara University.

Walter Ng Senior Director, Platform Alliances Chartered Semiconductor Manufacturing

Mr. Ng is responsible for developing and executing customer and partner alliances that advance the adoption of Chartered's solutions for leading-edge and mainstream technology nodes. He has led the company's collaboration with IBM and Samsung to define the strategy and implementation of solutions for the common design enablement platform at 90 nm, 65 nm, and 45 nm. Previously, he was senior director of design solutions, responsible for Chartered's relationship with third-party EDA and IP partners. Mr. Ng has more than 15 years of experience in the electronic design industry.