Third-party IP such as PCI Express, SATA, and RapidIO enable the development of designs with high time-to-market needs. But who is accountable for the verification of the IP-your IP vendor, you, or your customer? This panel brings together IP vendor representatives and their ASIC customers to debate the virtues and challenges of verification. See the panelists address the following questions: Do the IP vendors rely on their customers to complete their verification? Do the IP users staff parallel verification efforts? Will the customers pay a high premium if the vendor were to certify their IP as "correct"? Will the vendors give money-back guarantees if the IP is not correct? Can we expect IP vendors to test all possible configurations without customer help? How do customers make a make-versus-buy decision?

Vigyan Singhal President and Chief Executive Officer Oski Technology

Dr. Singhal founded the formal verification EDA company Jasper Design Automation, where he was the president and CEO from 1999 to 2003, and chief technology officer until 2005. Earlier, he was a research scientist at Cadence Berkeley Labs. He was also an instructor for design verification classes at the University of California Santa Cruz. He received his Ph.D. from UC Berkeley, where he was a Regents scholar.

Prakash Bare Managing Director, India Operations Rambus

Prior to joining Rambus, Mr. Bare was vice president of the IP business unit at GDA Technologies, a leading EDS and SIP company. He held various engineering and business positions during his 15 years in design automation and reuse industry. He worked at Cadence Design Systems and Cypress Semiconductor before co-founding GDA Technologies in 1996. He holds a master's degree in microelectronics from the Indian Institute of Technology in Kanpur.

Nagendra Cherukupalli Vice President Cypress Semiconductor

Dr. Cherukupalli manages a 140-engineer team across four design centers in the United States, India, and China. Current responsibilities include delivering on chip commitments to customers and managing the teams to success. His key contributions include starting two design centers for Cypress in India and China and promoting Cypress brand via keynotes, panels, press conferences, and articles. He has held various technical and managerial positions at AT&T Bell Laboratories, Cadence Design Systems, and Silicon Value, a fabless ASIC start-up in Silicon Valley. He has more than 21 years of experience in chip design and software development, backed by a Ph.D. in computer science from IIT in Chicago, Illinois.

Harry Foster Principal Engineer Mentor Graphics

Mr. Foster is chair of the IEEE 1850 Property Specification Language (PSL) working group. He is co-author of multiple verification books on subjects such as assertion-based design. He was chief architect at Verplex Systems and chief methodologist at Jasper Design Automation. He is the original creator of the Accellera Open Verification Library (OVL) assertion monitor standard and was the recipient of the Accellera 2006 Technical Excellence Award for his contribution to industry standards.

John Goodenough Director of Design Technology ARM

Dr. Goodenough is responsible for all aspects of design methodology, including support for ARM's internal production and deployment. He also works extensively with ARM's design partners and customers. Dr. Goodenough began his career as a Sheffield University research fellow, investigating novel VLSI signal processing architectures. He then co-founded Infinite Designs, specializing in advanced ASIC and embedded system design methodologies. A board member of Accellera and Si2 and a founding member of SPIRIT, Dr. Goodenough has a B.S. from Durham University and a Ph.D. in VLSI design from Sheffield University.

Ralph Morgan Senior Research and Development Director Synopsys

Mr. Morgan has spent more than 10 years with Synopsys working on DesignWare IP. In his current role, he is one of two senior R&D directors managing all aspects of IP development at Synopsys. His responsibilities include soft IP development methodology and all Synopsys soft IP titles except for the USB family.

Kathy Werner President VSI Alliance Reuse Manager Freescale Semiconductor

Ms. Werner has led the industry in its quest for IP standards for many years. She is the president of the VSI Alliance, the leading industry organization for IP standards. She has chaired the VSI Alliance Quality IP Pillar for the past six years; during this time, the first Quality IP (QIP) Metric was introduced. Ms. Werner is also working with the FSA and other industry organizations to extend this metric. As the Freescale Semiconductor reuse manager, Ms. Werner is responsible for IP coordination, standardization, and quality, including Freescale's interaction with the Spirit organization, a group that is also involved in SoC and IP issues. Ms. Werner is also the chair for the DesignCon IP Business and Engineering Impacts track.