High-speed serial link design and design methodology is an interesting and challenging topic. Case studies of SerDes I/O and channel design have been well attended in past DesignCon conferences. Hardware designers and signal integrity engineers need to make tradeoffs between cost, performance, time to market, and reliability. Good engineers use all of their experience, simulation tools, and measurement equipment to design high-speed links to function reliably with acceptable BERs. Engineers need to make a conscious effort to avoid analysis paralysis while meeting hard design ship criteria (i.e., cost, performance, reliability, schedule). While time domain techniques were prominent in the past, frequency domain is becoming the standard to design these links.

This panel of experts with academic and practical backgrounds in various areas of expertise will explore best design practice and methodologies for designing high-speed series links. They will discuss the advantages and disadvantages of time and frequency domain techniques to effectively solve this design challenge and share their experiences, successes, and failures.

Robert Haller Hardware Architect Enterasys Networks

Mr. Haller has more than 25 years of experience designing and analyzing complex modules, backplanes, packages, and integrated circuits. His first DesignCon paper won Outstanding Demonstration Linked to a Paper Award at DesignCon 1998. He also co-wrote the Best Paper at DesignCon 2003. His responsibilities at Enterasys include electromagnetic modeling, system-level signal integrity simulation, and the definition and design of a next-generation backplane. Mr. Haller previously worked at SiSoft and Cereva Networks and spent 19 years at Digital Equipment Corporation, where he achieved the level of senior member of technical staff. He chaired a panel at DesignCon East 2005 on Integrating Crosstalk, Timing, and Signal Integrity and served on DesignCon panels in 1998 and 2004. Mr. Haller received his B.S.E.E. degree from the University of Massachusetts.

Eric Bogatin President Bogatin Enterprises

Mr. Bogatin received his B.S. in physics from MIT and M.S. and Ph.D. in physics from the University of Arizona in Tucson. He has held senior engineering and management positions at Bell Labs, Raychem, Sun Microsystems, Ansoft, and Interconnect Devices. Eric has written four books on signal integrity and interconnect design and more than 200 papers. His latest book, Signal Integrity — Simplified, was published in 2004 by Prentice Hall. He has taught more than 4,000 engineers in the past 20 years.

Chris Heard Hardware System Architect Amphenol TCS

Mr. Heard has more than 20 years of experience in electronics packaging and high-speed backplane design. Prior to joining Amphenol in 2002, he spent 11 years designing backplanes, chassis, and cooling systems for networking and storage companies. He holds patents on chassis level cooling, EMI containment, and disk drive packaging.

Scott McMorrow Director of Engineering TeraSpeed Consulting

Mr. McMorrow is an experienced technologist with over 20 years of broad background in complex system design, interconnect and Signal Integrity engineering, modeling and measurement methodology, engineering team building and professional training. He has a consistent history of delivering and managing technical consultation that enables clients to manufacture systems with state-of-the-art performance, enhanced design margins, lower cost, and reduced risk. Mr. McMorrow is a expert consultant and trainer in high performance design and Signal Integrity engineering recognized worldwide.

Edward Sayre President and Chief Executive Officer North East Systems Associates

Dr. Sayre founded North East Systems Associates in 1973. Since that time, Dr. Sayre and the NESA staff have helped bring many companies to market with their high-performance products, published and presented at numerous design conferences, and contributed to a variety of technical publications.

Michael Steinberger Distinguished Member, Technical Staff SiSoft

Dr. Steinberger has more than 29 years of experience designing very-high-speed electronic circuits. Before joining SiSoft, Dr. Steinberger led a group at Cray, Inc., performing SerDes design, high-speed channel analysis, PCB design, and custom RAM design. At Cray, he drove development of methodologies and software used to successfully design and validate 6+ Gbps serial links. He has a Ph.D. and has been awarded seven patents.