As serial data rates climb, new validation challenges emerge. It is becoming more important to predict conclusive results at the serial receiver. Transmitter signal equalization efforts are being made in DSP to improve PHY signal performance. How to characterize and predict the appropriate level of performance during the design phase is challenging. This year's panel will discuss these measurement challenges and highlight some of the latest test methods leading to designs with more predictable receiver performance.

This TecForum panel, consisting of industry-leading design engineers who work on high-speed serial data designs and jitter application engineers from test and measurement companies, will provide you with design insights and spur active audience discussion around high-speed serial and jitter measurement approaches.

Chris J. Loberg Senior Marketing Manager Tektronix

Mr. Loberg is a senior manager of marketing for the design and manufacturing channel at Tektronix. In an earlier role with the company, Mr. Loberg was responsible for marketing management of optical communications test products at Tektronix. Prior to his stint at Tektronix, Chris was vice president of marketing for Utah Scientific, a manufacturer of telecom switching equipment; and vice president of sales and marketing for Texscan, a manufacturer of cable TV infrastructure equipment. He holds an M.B.A. in marketing from San Jose State University.

Joseph Diepenbrock Senior Technical Staff Member IBM

Mr. Diepenbrock has been with IBM since 1976 and has worked in a number of areas, including bipolar and CMOS IC design, analog and digital circuit design, backplane design and simulation, and network hardware and server product development. He is working on the electrical testing and modeling of connectors and cables. This work involves hardware testing and software simulation of various interconnect structures, lossy model generation and verification, and development of electrical test procedures and software.

Greg D. Le Cheminant Measurement Applications Specialist, Digital Signal Analysis Division Agilent Technologies

Mr. Le Cheminant is responsible for product management and development of new measurement applications for the division's digital communications analyzer and jitter test products. He represents Agilent on several industry standards committees. Mr. Le Cheminant has more than 20 years of experience at Agilent/Hewlett-Packard, including five years in manufacturing engineering and more than 15 years in various product marketing positions. He is a contributing author to four textbooks on high-speed digital communications and has written numerous technical articles on test-related topics.

Dr. Mike Li Chief Technology Officer Wavecrest

Dr. Li is pioneered jitter separation method (Tailfit) and DJ, RJ, and TJ concept and theory formation. He has involved in setting and contributed to standards for jitter, noise, and signal integrity for leading serial data communications, such as Fibre Channel, gigabit Ethernet, serial ATA, and PCI-Express. He is the co-chairman of the PCI-Express jitter standard committee. Dr. Li is sitting on the technical committees for IEEE- and IEC-sponsored technical conferences such as International Test Conference and DesignCon and is a regular speaker, panelist, and session and panel chair on the subjects of jitter/noise and signal integrity.

Mark Marlett Principal Design Engineer LSI Logic

Mr. Marlett has been designing, validating, and characterizing serial interface physical-layer transceivers and phase-locked loops for Fibre Channel, SONET, PCIE, SATA, and data moving backplanes since 1991. After he received an M.S.E.E. in 1989 from University of Illinois at Urbana-Champaign, Mr. Marlett started working at Cypress Semiconductor. In 2003, he joined LSI Logic's High Speed Interface Engineering (HSIE) organization as a principal design engineer.

Andrew Martwick Circuit Architect, Chipset Division Intel

Mr. Martwick recently wrote sections of the 3GIO physical-layer specification and co-chairs the PCI Express Jitter Working Group. He has more than 20 years of product design experience in software, hardware, and embedded systems and has more than 20 patents issued or pending in computer architecture and communications.

Marty Miller Chief Scientist LeCroy

Dr. Miller has been a hands-on engineer and designer at LeCroy for 29 years. He has contributed analog, digital, and software designs, and in the past 16 years, he has focused on measurement-and-display software capabilities for LeCroy scopes. Dr. Miller holds several U.S. patents and participates in task groups for JEDEC concerning jitter measurements. He has a doctorate in high-energy physics from the University of Rochester in Rochester, New York.

Dr. Kalev Sepp Applications Design Engineer Tektronix

Dr. Sepp specializes in high-speed serial data measurements and related signal processing. He joined Tektronix in 2001 and is working with signal integrity analysis and compliance testing software. He is a member of the InfiniBand TA and PCI-Express jitter standardization committee. Dr. Sepp was awarded a Ph.D. in electrical engineering from the University of Washington in Seattle in 2001. He has more than 15 years of control systems and DSP experience. He has one patent related to high-speed signal measurements.

Ransom Stephens Research Scientist Teraspeed Consulting

Dr. Stephens specializes in the analysis and documentation of electrodynamics in high-rate digital systems. He has served on the electrical working groups for many of the high-data-rate standards and has spent the past six years analyzing timing noise and dispersion and developing new techniques for extracting signals from noise. He started his career in basic-research laboratories across the United States and Europe making precise measurements of rare processes. He received his Ph.D. in physics from the University of California, Santa Barbara in 1990.