DesignCon 2007

By Date | By Track

Keynotes

Monday, January 29

Noon – 1:00 pm

Monday TecForum Luncheon Keynote

Steve Polzin, Senior Fellow and Chief Platform Architect, AMD

Tuesday, January 30

Noon – 12:30 pm

Tuesday Keynote Address

Willem P. "Wim" Roelandts, President, Chief Executive Officer and Chairman of the Board, Xilinx

Wednesday, January 31

Noon – 12:30 pm

Wednesday Keynote Address

Leah Jamieson, Associate Dean, Purdue University

DesignCon Business Forum

Tuesday, January 30

8:30 am – 10:00 pm

Business Forum Panel

Keeping It Cool: Strategies and Considerations for Dealing with Thermal Performance

10:15 am – 11:45 am

Business Forum Panel

Putting the "D" Back into DFM

2:00 pm – 3:30 pm

Business Forum Panel

Life Begins at 65-Especially for Mixed Signal

3:45 pm - 5:00 pm

Business Forum Panel

Memory Needs and Options for Consumer Products

Wednesday, January 31

8:45 am – 9:25 am

BF-WA1

Product Stewardship Model

8:45 am – 10:20 am

Business Forum Panel

The Business Impact of IP Quality on Market Growth: Freeing the Genie

9:40 am – 10:20 am

BF-WA2

Controlling Cost in the Design Process of Complex Systems

10:30 am –11:45 am

Business Forum Panel

Why Are We Still Designing Like It's 1992?

2:00 pm – 3:30 pm

Business Forum Panel

IP Selection 101 - Picking and Choosing the Right IP for Your Next Chip

3:45 pm – 5:00 pm

Business Forum Panel

DFM: Can Designers Afford NOT to Do It at 65 nm?

Technical Panels

Monday, January 29

4:45 pm – 6:00 pm

Technical Panel

Jitter and Its Challenges When Testing Serial Data Designs

Technical Panel

Controlled-ESR Bypass Capacitors: Myths and Truths

Tuesday, January 30

3:45 pm – 5:00 pm

Technical Panel

Best Design Practice and Methodologies for High-Speed Serial Links

Technical Panel

Emerging Challenges of DC-DC Converters

Technical Panel

Selecting the Right Encryption Technique for Securing Silicon IP

Wednesday, January 31

3:45 pm – 5:00 pm

Technical Panel

How to Hit a Moving Target: Or, How to Design to a Process When the Process Won't Stand Still

Technical Panel

Who Verifies Your Third-Party Design IP?

Technical Panel

Limitations of Simulation Techniques and Proper Model Validation for Both Signal Integrity and EMC

TecForums

Monday, January 29

9:00 am – Noon

TF-MA1

ESL - A Methodology for Handling Complexity

TF-MA2

Advances in Gigabit Channel Measurement-Based Characterization and Simulation

TF-MA3

Serial Data Equalization

1:30 pm – 4:30 pm

TF-MP1

Debugging Live FPGAs Using Synthesizable SystemVerilog Assertions

TF-MP2

Recent Developments in Jitter and Signal Integrity Measurement and Analysis

TF-MP3

Controlled-ESR Bypass Capacitors Have Arrived

TF-MP4

10 Gb Ethernet: Optical and Copper Interconnects, Standards, Tradeoffs, Business Choices

Thursday, February 1

9:00 am – 12:00 pm

TF-THA1

Fast and Accurate Assessments of Die Size, Power, and Cost of Different Libraries to Select the Best IP Solution for Mobile Applications

TF-THA2

Reconfigurable Computing for High-Performance Systems

Technology Exhibition

Tuesday, January 30

12:30 pm – 2:00 pm

Technology Exhibition | (Lunch served on Exhibition Floor)

Wednesday, January 31

12:30 pm - 2:00 pm

Technology Exhibition | (Lunch served on Exhibition Floor)

Track 1 | Application-Specific Design

Tuesday, January 30

10:15 am – 10:55 am

1-TA3

Selection Criteria for Using DDR, GDDR, or MobileDDR Memories in System Designs

11:05 am – 11:45 am

1-TA4

Low-Latency PCI-Express Impacts System Architecture Tradeoffs

2:00 pm – 2:40 pm

1-TP1

High-Performance Image Interfaces in Low-Cost Programmable Logic

2:50 pm – 3:30 pm

1-TP2

Optimizing Memory Interfaces for Specific Applications

Wednesday, January 31

8:45 am – 9:25 am

1-WA1

Unifying Residential Systems — Wired versus Wireless Infrastructures

9:40 am – 10:20 am

1-WA2

Comparison of a 1x Clock DDR Design versus a 2x Clock DDR Design

2:00 pm – 2:40 pm

1-WP1

Acceptance Criteria for a High-Definition Video Encoder

2:50 pm - 3:30 pm

1-WP2

Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2

Track 2 | Chip-Level Functional Design

Tuesday, January 30

8:30 am – 9:10 am

2-TA1

Architectural Requirements of an Oversubscribed Ethernet MAC

9:20 am - 10:00 am

2-TA2

Request-Response Trace for Bus Performance Analysis

2:00 pm – 2:40 pm

2-TP1

Creating a Generic Behavioral Model: DDR-Based Memory System Using SystemC/TLM

2:50 pm – 3:30 pm

2-TP2

IP Solves the Increasing Challenge of Implementing an Interface to Off-Chip DDR SDRAM

Wednesday, January 31

9:40 am – 10:20 am

2-WA2

FPGA Design for Signal and Power Integrity

Track 3 | Functional Verification

Tuesday, January 30

8:30 am – 9:10 am

3-TA1

ASIC Functional Signoff in Equivalence Checker

9:20 am – 10:00 am

3-TA2

Building Verification IP for Reusability � Based on SystemVerilog and TLM Standards

10:15 am – 10:55 am

3-TA3

Guidelines for SystemVerilog Assertions and Functional Coverage

11:05 am – 11:45 am

3-TA4

UltraSPARC Processor Emulation Verification: Getting SW/HW Right the First Time!

2:00 pm – 2:40 pm

3-TP1

Serial Protocol Compliance of a FPGA-Integrated Mixed-Signal Transceiver

2:50 pm – 3:30 pm

3-TP2

Dissecting Multimillion Gate Design Bugs

Wednesday, January 31

8:45 am – 9:25 am

3-WA1

PHY Verification - Still an Open Problem

9:40 am – 10:20 am

3-WA2

Planning Formal Verification Closure

2:00 pm – 2:40 pm

3-WP1

SPECIAL SESSION: Using SystemVerilog to Ensure a Quality Transition to Randomized Tests

2:50 pm – 3:30 pm

3-WP1 (cont.)

SPECIAL SESSION: Using SystemVerilog to Ensure a Quality Transition to Randomized Tests

Track 4 | Chip-Level Physical Design and Verification

Tuesday, January 30

9:20 am – 10:00 am

4-TA2

Methodology to Analyze and Insert a Power Mesh Early in the Design Cycle

10:15 am – 10:55 am

4-TA3

Calibration Techniques for High-Bandwidth Source Synchronous Interfaces

11:05 am – 11:45 am

4-TA4

RFID Radio Circuit Design in CMOS

Wednesday, January 31

2:00 pm – 2:40 pm

4-WP1

Practical Clock Skew Scheduling on a High-Performance Processor

2:50 pm – 3:30 pm

4-WP2

Moving Manufacturing More Effectively into Design

Track 5 | Chip and Package Co-Design

Tuesday, January 30

2:00 pm – 2:40 pm

5-TP1

Selecting the Best Package Type for Your Design — Today and Tomorrow

2:50 pm – 3:30 pm

5-TP2

Nonlinear Behavior of Switching Noise in FPGA CMOS Devices, Physical Mechanism, Simulation Methodology, and Measurement Correlation

Wednesday, January 31

2:00 pm – 2:40 pm

5-WP1

Packaging a Supercomputer in the PCIe Form Factor

Track 6 | PCB and Package Technologies

Tuesday, January 30

8:30 am – 9:10 am

6-TA1

The Role of Dielectric Constant and Dissipation Factor Measurements in Multi-Gigabit Systems

9:20 am – 10:00 am

6-TA2

Fiberweave Effect: Practical Impact Analysis and Mitigation Strategies

10:15 am – 10:55 am

6-TA3

Developing a "Physical" Model for Vias - Part II: Coupled and Ground Return Vias

11:05 am – 11:45 am

6-TA4

Compact Electromagnetic Bandgap Structures for Power-Plane Isolation Using High-K Dielectrics

Track 7 | Multi-Gigabit Interconnects

Tuesday, January 30

8:30 am – 9:10 am

7-TA1-1

Class F_A High-Speed Interconnects

7-TA1-2

Crosstalk Due to Periodic Plane Cutouts

9:20 am – 10:00 am

7-TA2

SPICE Modeling of a Backplane to Daughtercard Link from an EM Simulation Environment

10:15 am – 10:55 am

7-TA3

Advanced Design Techniques to Support Next-Generation Backplane Links beyond 10 Gbps

11:05 am – 11:45 am

7-TA4-1

Improving the Reach-Gauge Tradeoff in Copper Cable Interconnects

7-TA4-2

Improving System Performance by Reducing System Impedance to 85 Ohms

2:00 pm – 2:40 pm

7-TP1

Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk

2:50 pm – 3:30 pm

7-TP2

Losses Induced by Asymmetry in Differential Transmission Lines

Wednesday, January 31

8:45 am – 9:25 am

7-WA1

TDR and S-parameter Measurements for Serial Data Applications: How Much Rise Time, Bandwidth, and Dynamic Range Do You Need?

9:40 am – 10:20 am

7-WA2

Artificial Card-Edge Interfaces for 10 Gbps Module Cards: How the High-Speed Propagation Characteristics Are Affected by Exchanging the PCB-Edge with a Connector

2:50 pm – 3:30 pm

7-WP2

10 G High-Speed Serial Ethernet

Track 8 | High-Speed Timing, Jitter, and Noise

Tuesday, January 30

8:30 am – 9:10 am

8-TA1

Precision Digital Noise Source

9:20 am – 10:00 am

8-TA2

PCB Design Methods for Optimum FPGA SerDes Jitter Performance

10:15 am – 10:55 am

8-TA3

Simultaneous Jitter Analysis in Time, Frequency, and Statistical Domains and Their Interrelationships

11:05 am – 11:45 am

8-TA4

Real-Time Sampling Technique Affects Accuracy of High-Speed Digital Measurements

2:00 pm – 2:40 pm

8-TP1

Transport Delay and Jitter Measurements Based on Cross-Correlation on Real-Time Oscilloscopes

2:50 pm – 3:30 pm

8-TP2

Accurate Method for Analyzing High-Speed I/O System Performance

Wednesday, January 31

8:45 am – 9:25 am

8-WA1

Single-Simulation Analysis of a DDR2 Interface in IBIS 4.1

9:40 am – 10:20 am

8-WA2

Method of BER Analysis of High-Speed Serial Data Transmission in Presence of Jitter and Noise

2:00 pm – 2:40 pm

8-WP1

A Comparison of Methods for Estimating Total Jitter Concerning Precision, Accuracy, and Robustness

2:50 pm – 3:30 pm

8-WP2

Pre-Emphasis and Equalization Parameter Optimization with Fast, Worst-Case/Multibillion-Bit Verification

Track 9 | High-Speed Signal Processing, Equalization and Coding

Tuesday, January 30

8:30 am – 9:10 am

9-TA1

Analog CMOS Equalizer Circuits for 10 Gbps Serial Data Transmission

9:20 am – 10:00 am

9-TA2

Equalization Challenges for 6 Gbps Transceivers Addressed by PELE—A Software—Focused Solution

10:15 am – 10:55 am

9-TA3

Performance Comparison of Edge-Based Equalization and Data-Based Equalization for Transmitter and Receiver

11:05 am – 11:45 am

9-TA4

Comparison of Signaling and Equalization Schemes in High-Speed SerDes over 6 Gbps

2:00 pm – 2:40 pm

9-TP1

Digitally Assisted Adaptive Equalizers in 90 nm with Wide-Range Support from 2.5 Gbps to 6.5 Gbps

Track 10 | Passive Component Characterization and Modeling

Tuesday, January 30

9:20 am – 10:00 am

10-TA2

Signal Integrity Analysis for Inductively Coupled Connectors and Sockets

2:00 pm – 2:40 pm

10-TP1

Applications of Optimization Routines in Signal Integrity Analysis

2:50 pm – 3:30 pm

10-TP2

Methodology to Generate Frequency Domain Specifications from Eye Masks Using Statistical Analysis

Wednesday, January 31

8:45 am – 9:25 am

10-WA1

Impulse Response Characterization of Operating Margin in High-Speed Communication Channels

9:40 am – 10:20 am

10-WA2

Differential PCB Structures Using Measured TRL Calibration and Simulated Structure De-Embedding

2:00 pm – 2:40 pm

10-WP1

Comparison of S-Parameter Concatenation to Full-Wave Simulation for High-Speed Interconnect Analysis

2:50 pm – 3:30 pm

10-WP2

Application of Embedded Capacitor Technology for High-Performance Semiconductor Packaging

Track 11 | Power Integrity and Power-Aware Design

Tuesday, January 30

10:15 am – 10:55 am

11-TA3

Power Supply Compensation for Capacitive Loads

2:00 pm – 2:40 pm

11-TP1

Electromagnetic Bandgap Structures for Parallel Plate Waveguide Noise Suppression in PWR/GND Plane Pairs

2:50 pm – 3:30 pm

11-TP2

Common Mode Radiation of a Printed Circuit Board with Embedded Decoupling Capacitor Excited by IC's Shoot-Through Current

Wednesday, January 31

8:45 am – 9:25 am

11-WA1

Analysis of Supply Noise-Induced Jitter in Gigabit I/O Interfaces

9:40 am – 10:20 am

11-WA2

Study of Simultaneous Switching Noise Reduction for Microprocessor Packages by Application of High-K MIM Decoupling Capacitors

2:00 pm – 2:40 pm

11-WP1

Characterization and Output Filter Optimization Methods for Voltage Regulator Modules

2:50 pm – 3:30 pm

11-WP2

Power Network Synthesis of Power-Gating Designs

Track 12 | Electromagnetic Compatibility and Interference

Tuesday, January 30

8:30 am – 9:10 am

12-TA1

A Study on Radiation from Pentium Clock Generator ICs

9:20 am – 10:00 am

12-TA2

Novel Band-Stop Common Mode Filter for High-Speed Digital Data Transmission

10:15 am – 10:55 am

12-TA3

EMI Emissions from Mismatches in High-Speed Differential Signal Traces and Cables

11:05 am – 11:45 am

12-TA4

Comparing Time-Domain and Frequency-Domain Techniques for Investigation on Charge Delivery and Power-Bus Noise for High-Speed Printed Circuit Boards

Track 13 | Test Fixturing and Measurement Methodology

Tuesday, January 30

8:30 am – 9:10 am

13-TA1

Meaningful Measurement of Differential Transmission Line Skew at 10 Gbps and Above

2:50 pm – 3:30 pm

13-TP2

A Generic and Higher Order Model for High-Speed Test Interface Analysis and De-embedding

Wednesday, January 31

8:45 am – 9:25 am

13-WA1

A Method for Testing Jitter Tolerance of SerDes Receivers Using Random Jitter

9:40 am – 10:20 am

13-WA2

Architectural Considerations for Multiport Vector Network Analyzers

2:00 pm – 2:40 pm

13-WP1

Design and Test Challenges Facing Next-Generation 20 Gbps Interconnects

2:50 pm – 3:30 pm

13-WP2

A Novel Procedure for Characterization of Multiport High-Speed Balanced Devices