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Tuesday, January 30

8:30 am – 9:10 am

2-TA1 | Architectural Requirements of an Oversubscribed Ethernet MAC

3-TA1 | ASIC Functional Sign-Off in Equivalence Checker

6-TA1 | The Role of Dielectric Constant and Dissipation Factor

7-TA1-1 | Class F_A High-Speed Interconnects

7-TA1-2 | Crosstalk Due to Periodic Plane Cutouts

8-TA1 | Precision Digital Noise Source

9-TA1 | Analog CMOS Equalizer Circuits for 10 Gbps Serial Data Transmission

12-TA1 | A Study on Radiation from Pentium Clock Generator ICs

13-TA1 | Meaningful Measurement of Differential Transmission Line Skew at 10 Gbps and Above

8:30 am – 10:00 am

Business Forum Panel | Keeping It Cool: Strategies and Considerations for Dealing with Thermal Performance

9:20 am – 10:00 am

2-TA2 | Request-Response Trace for Bus Performance Analysis

3-TA2 | Building Verification IP for Reusability - Based on SystemVerilog and TLM Standards

4-TA2 | Methodology to Analyze and Insert a Power Mesh Early in the Design Cycle

6-TA2 | Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies

7-TA2 | SPICE Modeling of a Backplane to Daughtercard Link from EM Simulation Environment

8-TA2 | PCB Design Methods for Optimum FPGA SerDes Jitter Performance

9-TA2 | Equalization Challenges for 6 Gbps Transceivers Addressed by PELE—A Software—Focused Solution

10-TA2 | Signal Integrity Analysis for Inductively Coupled Connectors and Sockets

12-TA2 | Novel Band-Stop Common Mode Filter for High-Speed Digital Data Transmission

10:00 am – 10:15 am

Networking Break

10:15 am – 10:55 am

1-TA3 | Selection Criteria for Using DDR, GDDR, or MobileDDR Memories in System Designs

3-TA3 | Guidelines for SystemVerilog Assertions and Functional Coverage

4-TA3 | Calibration Techniques for High-Bandwidth Source Synchronous Interfaces

6-TA3 | Developing a "Physical" Model for Vias - Part II: Coupled and Ground Return Vias

7-TA3 | Advanced Design Techniques to Support Next-Generation Backplane Links Beyond 10 Gbps

8-TA3 | Simultaneous Jitter Analysis in Time, Frequency, and Statistical Domains and Their Interrelationships

9-TA3 | Performance Comparison of Edge-Based Equalization and Data-Based Equalization for Transmitter and Receiver

11-TA3 | Power Supply Compensation for Capacitive Loads

12-TA3 | EMI Emissions from Mismatches in High-Speed Differential Signal Traces and Cables

10:15 am – 11:45 am

Signal Integrity Workshop

Business Forum Panel | Putting the "D" Back into DFM

11:05 am – 11:45 am

1-TA4 | Low-Latency PCI-Express Impacts System Architecture Tradeoffs

3-TA4 | UltraSPARC Processor Emulation Verification: Getting SW/HW Right the First Time!

4-TA4 | RFID Radio Circuit Design in CMOS

6-TA4 | Compact Electromagnetic Bandgap Structures for Power Plane Isolation Using High-K Dielectrics

7-TA4-1 | Improving the Reach-Gauge Tradeoff in Copper Cable Interconnects

7-TA4-2 | Improving System Performance by Reducing System Impedance to 85 Ohms

8-TA4 | Real-Time Sampling Technique Affects Accuracy of High-Speed Digital Measurements

9-TA4 | Comparison of Signaling and Equalization Schemes in High-Speed SerDes over 6 Gbps

12-TA4 | Comparing Time-Domain and Frequency Domain Techniques for Investigation on Charge Delivery and Power-Bus Noise for High-Speed Printed Circuit Boards

12:00 pm – 12:30 pm

Tuesday Keynote Address

Speaker: Willem P. "Wim" Roelandts, President, Chief Executive Officer, and Chairman of the Board, Xilinx

DesignVision Awards to Be Presented at Keynote Address

12:30 pm – 2:00 pm

Lunch served on Exhibition Floor

12:30 pm – 6:30 pm

Technology Exhibition

2:00 pm – 2:40 pm

1-TP1 | High-Performance Image Interfaces in Low-Cost Programmable Logic

2-TP1 | Creating a Generic Behavioral Model: DDR-Based Memory System Using SystemC/TLM

3-TP1 | Serial Protocol Compliance of a FPGA Integrated Mixed Signal Transceiver

5-TP1 | Selecting the Best Package Type for Your Design — Today and Tomorrow

7-TP1 | Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk

8-TP1 | Transport Delay and Jitter Measurements Based on Cross-Correlation on Real-Time Oscilloscopes

9-TP1 | Digitally Assisted Adaptive Equalizers in 90 nm with Wide-Range Support from 2.5 Gbps to 6.5 Gbps

10-TP1 | Applications of Optimization Routines in Signal Integrity Analysis

11-TP1 | Electromagnetic Bandgap Structures for Parallel Plate Waveguide Noise Mitigation in PWR/GND Plane Pairs

2:00 pm – 3:30 pm

Business Forum Panel | Life Begins at 65-Especially for Mixed Signal

2:50 pm – 3:30 pm

1-TP2 | Optimizing Memory Interfaces for Specific Applications

2-TP2 | IP Solves the Increasing Challenge of Implementing an Interface to Off-Chip DDR SDRAM

3-TP2 | Dissecting Multimillion Gate Design Bugs

5-TP2 | Nonlinear Behavior of Switching Noise in FPGA CMOS Devices, Physical Mechanism, Simulation Methodology, and Measurement Correlation

7-TP2 | Losses Induced by Asymmetry in Differential Transmission Lines

8-TP2 | Accurate Method for Analyzing High-Speed I/O System Performance

10-TP2 | Methodology to Generate Frequency Domain Specifications from Eye Masks Using Statistical Analysis

11-TP2 | Common Mode Radiation of a Printed Circuit Board with Embedded Decoupling Capacitor Excited by IC's Shoot-Through Current

13-TP2 | A Generic and Higher-Order Model for High-Speed Test Interface Analysis and De-Embedding

3:30 pm – 3:45 pm

Networking Break

3:45 pm – 5:00 pm

Technical Panel | Best Design Practice and Methodologies for High-Speed Serial Links

Technical Panel | Emerging Challenges of DC-DC Converters

Technical Panel | Selecting the Right Encryption Technique for Securing Silicon IP

Business Forum Panel | Embedded Memory Needs and Options for Consumer Products

5:00 pm – 6:30 pm

Reception on the Exhibition Floor

Poster Session on Exhibits Floor