DesignCon 2007

Connecting the World of Electronic Design

Below please find all room locations for paper, forums, and panels being presented at DesignCon 2007.

Please note: A dedicated speaker preparation room will be available to all speakers in room 211. Speakers are welcome to use the speaker preparation room for on-site preparation meetings with their panelists.

Monday, January 29

9:00 am – 12:00 pm
SESSION/TITLE	LOCATION
TF-MA1 \| ESL — A Methodology for Handling Complexity	H
TF-MA2 \| Advances in Gigabit Channel Measurement-Based Characterization and Simulation	G
TF-MA3 \| Serial Data Equalization	F

12:00 pm – 1:00 pm
SESSION/TITLE	LOCATION
Monday TecForum Luncheon Keynote \| Speaker: Steve Polzin, Senior Fellow and Chief Platform Architect, AMD	Great American Ballroom

1:30 pm – 4:30 pm
SESSION/TITLE	LOCATION
TF-MP1 \| Debugging Live FPGAs Using Synthesizable SystemVerilog Assertions	H
TF-MP2 \| Recent Developments in Jitter and Signal Integrity Measurement and Analysis	G
TF-MP3 \| Controlled-ESR Bypass Capacitors Have Arrived	F
TF-MP4 \| 10 Gb Ethernet: Optical and Copper Interconnects, Standards, Tradeoffs, Business Choices	E

4:45 pm – 6:00 pm
SESSION/TITLE	LOCATION
Technical Panel \| Jitter and Its Challenges When Testing Receivers Used in Serial Data Designs	E and F
Technical Panel \| Controlled-ESR Bypass Capacitors: Myths and Truths	H and G

Tuesday, January 30

8:30 am – 9:10 am
SESSION/TITLE	LOCATION
2-TA1 \| Architectural Requirements of an Oversubscribed Ethernet MAC	212
3-TA1 \| ASIC Functional Sign-Off in Equivalence Checker	209 – 210
6-TA1 \| The Role of Dielectric Constant and Dissipation Factor	E
7-TA1-1 \| Class F_A High-Speed Interconnects	201
7-TA1-2 \| Crosstalk Due to Periodic Plane Cutouts	F
8-TA1 \| Precision Digital Noise Source	G
9-TA1 \| Analog CMOS Equalizer Circuits for 10 Gbps Serial Data Transmission	H
12-TA1 \| A Study on Radiation from Pentium Clock Generator ICs	206
13-TA1 \| Meaningful Measurement of Differential Transmission Line Skew at 10 Gbps and Above	207

8:30 am – 10:00 am
SESSION/TITLE	LOCATION
Business Forum Panel \| Keeping It Cool: Strategies and Considerations for Dealing with Thermal Performance	203 – 204

9:20 am – 10:00 am
SESSION/TITLE	LOCATION
2-TA2 \| Request-Response Trace for Bus Performance Analysis	212
3-TA2 \| Building Verification IP for Reusability - Based on SystemVerilog and TLM Standards	209 – 210
4-TA2 \| Methodology to Analyze and Insert a Power Mesh Early in the Design Cycle	201
6-TA2 \| Fiber Weave Effect: Practical Impact Analysis and Mitigation Strategies	E
7-TA2 \| SPICE Modeling of a Backplane to Daughtercard Link from EM Simulation Environment	F
8-TA2 \| PCB Design Methods for Optimum FPGA SerDes Jitter Performance	G
9-TA2 \| Equalization Challenges for 6 Gbps Transceivers Addressed by PELE-A Software-Focused Solution	H
10-TA2 \| Signal Integrity Analysis for Inductively Coupled Connectors and Sockets	207
12-TA2 \| Novel Band-Stop Common Mode Filter for High-Speed Digital Data Transmission	206

10:15 am – 10:55 am

SESSION/TITLE LOCATION

1-TA3 | Selection Criteria for Using DDR, GDDR, or MobileDDR Memories in System Designs 212

3-TA3 | Guidelines for SystemVerilog Assertions and Functional Coverage 209 – 210

4-TA3 | Calibration Techniques for High-Bandwidth Source Synchronous Interfaces 201

6-TA3 | Developing a "Physical" Model for Vias - Part II: Coupled and Ground Return Vias E

7-TA3 | Advanced Design Techniques to Support Next-Generation Backplane Links Beyond 10 Gbps F

8-TA3 | Simultaneous Jitter Analysis in Time, Frequency, and Statistical Domains and Their Interrelationships G

9-TA3 | Performance Comparison of Edge-Based Equalization and Data-Based Equalization for Transmitter and Receiver H

11-TA3 | Power Supply Compensation for Capacitive Loads 207

12-TA3 | EMI Emissions from Mismatches in High-Speed Differential Signal Traces and Cables 206

10:15 am – 11:45 am

SESSION/TITLE LOCATION

Signal Integrity Workshop Great American Ballroom

Business Forum Panel | Putting the "D" Back into DFM 203 – 204

11:05 am – 11:45 am

SESSION/TITLE LOCATION

1-TA4 | Low-Latency PCI-Express Impacts System Architecture Tradeoffs 212

3-TA4 | UltraSPARC Processor Emulation Verification: Getting SW/HW Right the First Time! 209 – 210

4-TA4 | RFID Radio Circuit Design in CMOS 201

6-TA4 | Compact Electromagnetic Bandgap Structures for Power Plane Isolation Using High-K Dielectrics E

7-TA4-1 | Improving the Reach-Gauge Tradeoff in Copper Cable Interconnects 207

7-TA4-2 | Improving System Performance by Reducing System Impedance to 85 Ohms F

8-TA4 | Real-Time Sampling Technique Affects Accuracy of High-Speed Digital Measurements G

9-TA4 | Comparison of Signaling and Equalization Schemes in High-Speed SerDes over 6 Gbps H

12-TA4 | Comparing Time-Domain and Frequency Domain Techniques for Investigation on Charge Delivery and Power-Bus Noise for High-Speed Printed Circuit Boards 206

12:00 pm – 12:30 pm

SESSION/TITLE LOCATION

Tuesday Keynote Address | Speaker: Willem P. "Wim" Roelandts, President, Chief Executive Officer, and Chairman of the Board, Xilinx
DesignVision Awards to Be Presented at Keynote Address
Theater

2:00 pm – 2:40 pm

SESSION/TITLE LOCATION

1-TP1 | High-Performance Image Interfaces in Low-Cost Programmable Logic 212

2-TP1 | Creating a Generic Behavioral Model: DDR-Based Memory System Using SystemC/TLM 201

3-TP1 | Serial Protocol Compliance of a FPGA Integrated Mixed Signal Transceiver 209 – 210

5-TP1 | Selecting the Best Package Type for Your Design — Today and Tomorrow 206

7-TP1 | Impact of Backplane Connector Pin Field on Trace Impedance and Vertical Field Crosstalk F

8-TP1 | Transport Delay and Jitter Measurements Based on Cross-Correlation on Real-Time Oscilloscopes G

9-TP1 | Digitally Assisted Adaptive Equalizers in 90 nm with Wide-Range Support from 2.5 Gbps to 6.5 Gbps H

10-TP1 | Applications of Optimization Routines in Signal Integrity Analysis 207

11-TP1 | Electromagnetic Bandgap Structures for Parallel Plate Waveguide Noise Mitigation in PWR/GND Plane Pairs E

2:00 pm – 3:30 pm

SESSION/TITLE LOCATION

Business Forum Panel | Life Begins at 65-Especially for Mixed Signal 203 – 204

2:50 pm – 3:30 pm

SESSION/TITLE LOCATION

1-TP2 | Optimizing Memory Interfaces for Specific Applications 212

2-TP2 | IP Solves the Increasing Challenge of Implementing an Interface to Off-Chip DDR SDRAM 201

3-TP2 | Dissecting Multimillion Gate Design Bugs 209 – 210

5-TP2 | Nonlinear Behavior of Switching Noise in FPGA CMOS Devices, Physical Mechanism, Simulation Methodology, and Measurement Correlation 206

7-TP2 | Losses Induced by Asymmetry in Differential Transmission Lines F

8-TP2 | Accurate Method for Analyzing High-Speed I/O System Performance G

10-TP2 | Methodology to Generate Frequency Domain Specifications from Eye Masks Using Statistical Analysis 207

11-TP2 | Common Mode Radiation of a Printed Circuit Board with Embedded Decoupling Capacitor Excited by IC's Shoot-Through Current E

13-TP2 | A Generic and Higher-Order Model for High-Speed Test Interface Analysis and De-Embedding H

3:45 pm – 5:00 pm

SESSION/TITLE LOCATION

Technical Panel | Best Design Practice and Methodologies for High-Speed Serial Links E – F

Technical Panel | Emerging Challenges of DC-DC Converters G

Technical Panel | Selecting the Right Encryption Technique for Securing Silicon IP H

Business Forum Panel | Memory Needs and Options for Consumer Products 203 – 204

Wednesday, January 31

8:45 am – 9:25 am
SESSION/TITLE	LOCATION
1-WA1 \| Unifying Residential Systems — Wired versus Wireless Infrastructures	212
3-WA1 \| PHY Verification — Still an Open Problem	209 – 210
7-WA1 \| TDR and S-Parameter Measurements for Serial Data Applications: How Much Rise Time, Bandwidth, and Dynamic Range Do You Need?	F
8-WA1 \| Single-Simulation Analysis of a DDR2 Interface in IBIS 4.1	G
10-WA1 \| Impulse Response Characterization of Operating Margin in High-Speed Communication Channels	H
11-WA1 \| Analysis of Supply Noise Induced Jitter in Gigabit I/O Interfaces	E
13-WA1 \| A Method for Testing Jitter Tolerance of SerDes Receivers Using Random Jitter	206
BF-WA1 \| Product Stewardship Model	207

8:45 am – 10:20 am
SESSION/TITLE	LOCATION
Business Forum Panel \| The Business Impact of IP Quality on Market Growth: Freeing the Genie	203 – 204

9:40 am – 10:20 am
SESSION/TITLE	LOCATION
1-WA2 \| Comparison of a 1x Clock DDR Design versus a 2x Clock DDR Design	212
2-WA2 \| FPGA Design for Signal and Power Integrity	201
3-WA2 \| Planning Formal Verification Closure	209 – 210
7-WA2 \| Artificial Card-Edge Interfaces for 10 Gbps Module Cards: How the High-Speed Propagation Characteristics Are Affected by Exchanging the PCB Edge with a Connector	F
8-WA2 \| Method of BER Analysis of High-Speed Serial Data Transmission in Presence of Jitter and Noise	G
10-WA2 \| Differential PCB Structures Using Measured TRL Calibration and Simulated Structure De-Embedding	H
11-WA2 \| Study of Simultaneous Switching Noise Reduction for Microprocessor Packages by Application of High-K MIM Decoupling Capacitors	E
13-WA2 \| Architectural Considerations for Multiport Vector Network Analyzers	206
BF-WA2 \| Controlling Cost in the Design Process of Complex Systems	207

10:30 am – 11:45 am
SESSION/TITLE	LOCATION
Plenary Panel \| Why Are We Still Designing Like It's 1992?	Theater

12:00 pm – 12:30 pm
SESSION/TITLE	LOCATION
Wednesday Keynote Address \| Speaker: Leah Jamieson, John A. Edwardson Dean of Engineering, College of Engineering	Theater

2:00 pm – 2:40 pm
SESSION/TITLE	LOCATION
1-WP1 \| Acceptance Criteria for a High-Definition Video Encoder	212
3-WP1 \| SPECIAL SESSION: The Road to Verification Closure is Paved with Good Intentions	209 – 210
4-WP1 \| Practical Clock Skew Scheduling on a High-Performance Processor	201
5-WP1 \| Packaging a Supercomputer in a PCI Express Form Factor	207
7-WP1 \| Anticipating Inter-Symbol Interference of Signal Link on an FPGA System	F
8-WP1 \| A Comparison of Methods for Estimating Total Jitter Concerning Precision, Accuracy, and Robustness	G
10-WP1 \| Comparison of S-Parameter Concatenation to Full-Wave Simulation for High-Speed Interconnect Analysis	H
11-WP1 \| Characterization and Output Filter Optimization Methods for Voltage Regulator Modules	E
13-WP1 \| Design and Test Challenges Facing Next-Generation 20 Gbps Interconnects	206

2:00 pm – 3:30 pm
SESSION/TITLE	LOCATION
Business Forum Panel \| IP Selection 101 — Picking and Choosing the Right IP for Your Next Chip	203 – 204

2:50 pm – 3:30 pm
SESSION/TITLE	LOCATION
1-WP2 \| Memory Design Considerations when Migration to DDR3 Interfaces from DDR2	212
3-WP1 (cont.) \| SPECIAL SESSION: The Road to Verification Closure is Paved with Good Intentions	209 – 210
4-WP2 \| Moving Manufacturing More Effectively into Design	201
7-WP2 \| 10 G High-Speed Serial Ethernet	F
8-WP2 \| Pre-Emphasis and Equalization Parameter Optimization with Fast, Worst-Case/Multibillion Bit Verification	G
10-WP2 \| Application of Embedded Capacitor Technology for High-Performance Semiconductor Packaging	H
11-WP2 \| Power Network Synthesis of Power Gating Designs	E
13-WP2 \| A Novel Procedure for Characterization of Multiport High-Speed Balanced Devices	206

3:45 pm – 5:00 pm
SESSION/TITLE	LOCATION
Technical Panel \| How to Hit a Moving Target: Or, How to Design to a Process When the Process Won't Stand Still	H
Technical Panel \| Who Verifies Your Third-Party Design IP?	G
Technical Panel \| Limitations of Simulation Techniques and Proper Model Validation for Both Signal Integrity and EMC	E – F
Business Forum Panel \| DFM: Can Designers Afford NOT to Do It at 65 nm?	203 – 204

Thursday, February 1

9:00 am – 12:00 pm
SESSION/TITLE	LOCATION
TF-THA1 \| Fast and Accurate Assessments of Die Size, Power, and Cost of Different Libraries to Select the Best IP Solution for Mobile Applications	G
TF-THA2 \| Reconfigurable Computing for High-Performance Systems	F