To be presented at the Exhibitors' Reception on the Exhibits floor on Tuesday, January 30 and Wednesday, January 31 from 5:00 pm to 6:30 pm.
Jimmy Hsu, Deputy Manager, VIA Technologies
Eric Liao, Deputy Manager, VIA Technologies
The traditional simple electrical testing is hard to meet the industry requirement. In addition, at-speed wafer level testing by high-performance vertical probe card is becoming increasingly important in high-volume production to figure out the device speed limit and corresponding function. This testing methodology not only saves the expensive flip-chip substrate cost, but it also knows the device property distribution for the process improvement index. The electrical characteristics were specially designed, and the impedance, bandwidth of the entire interconnect, and testing wafer sorting result were measured and verified up to 1.6Gbps for the high-quality signal integrity consideration.
Barbara Aichinger, Vice President and Co-Founder, FuturePlus Systems
Connectorless probing is being widely adopted in order to non intrusively probe 1.25 Gb/s to 5.2 Gb/s serial interfaces. The footprints, or pads are incorporated onto the PCB and remain there for the life of the product thereby allowing easy and high performance testing in the lab, manufacturing, and the field. This new innovation offers several compelling reasons why designers should pursue it. First of all, the footprint or pad configurations are being standardized so that multiple vendors' test equipment can attach to them. This is a win for the industry, since engineers can design in one footprint at design time, and then pick the test equipment vendor when they are ready to test. Second, several high performance cable and connector vendors are adopting this technology which will drive down cost and increase innovation. Third, several serial standards are adopting the same footprint configuration thus allowing for design reuse and additional standardization for the various serial protocols. This paper will review the emergence of connectorless probing, its adoption to date, and its high performance characteristics that allow for serial interconnect protocol testing. Test cases involving PCI Express and Serial Rapid IO will be discussed.
Kyle Kauffman, Student, Miami University, Ohio
Gregg Trueb, Student, Miami University, Ohio
Dmitriy Garmatyuk, Assistant Professor, Miami University, Ohio
A method and its software implementation targeted at low-cost yet fast, accurate, and exhaustive analysis of high-speed data transfer topologies will be presented. The software, written by Miami University students in C, allows users to specify a data pattern, bit width, edge rates, and desired level of simulated jitter, then generates samples of resultant analog signal. The signal is then "passed" through interconnect model represented by either lab-extracted or modeled S-parameter files. Receiver-end processing includes eye-diagram generation with or without jitter and identification of potential interconnect design improvements if the eye diagram fails the specification template. Improvements over existing commercial software packages will be discussed.
Jimmy Hsu, Deputy Manager, VIA Technologies
Chin-Sung Lin, SI Engineer, VIA Technologies
System in package (SiP) design becomes paramount to integrating several components with different functions into a single systematic package for saving efficiently space and cost. However, this advanced integration could accompany serious signal and power integrity issue, such as crosstalk and high loop-inductance caused by the restricted routing and power shape in layer-limit package. Therefore, the electrical analysis needs to be performed on the design phase to prevent the baffling signal and power integrity problems and to speed up the marketing time. In this poster, one SiP with CPU and SOC was analyzed to find the peculiar weakness in the existing design, and the improvement will be proposed as the guideline for future applications.
