The DFM challenges associated with lithography and chemical mechanical polishing (CMP) mean that at 65 nm and below, what you draw is no longer what you get on silicon. This variability can result in both catastrophic and parametric yield loss.

How is DFM being introduced into design flows without requiring designers to suddenly become manufacturing engineers? Are the fabs/foundries providing adequate information? How can designers meet yield and parametric goals at 65 nm and below while fully utilizing process technologies and without sacrificing time to market?

Jim Hogan Private Investor

Mr. Hogan has worked in the semiconductor industry for more than three decades. His experience includes time as a senior executive in electronic design automation, semiconductor intellectual property, semiconductor equipment, and fabrication companies. Prior to joining Telos Venture Partners in 2004, Mr. Hogan was senior vice president of business development of Artisan Components. Previously, he was senior vice president of business development and the senior member of the office of the chief technologist at Cadence Design Systems. Mr. Hogan was a Cadence executive fellow and held several positions at Cadence, including president of Cadence Japan, corporate vice president of marketing, and corporate vice president for field operations. He was also chief operating officer of Smart Machines, Inc., a semiconductor equipment automation company. Mr. Hogan also worked for National Semiconductor and Philips.

Richard Brashears Corporate Vice President, Manufacturing Modeling and Implementation Technologies Cadence Design Systems

Since 2001, Mr. Brashears has focused on the development of sub-wavelength automated layout solutions, including two recently announced manufacturing aware routing products-the Cadence Chip Optimizer and the Cadence Space-Based Router. He has added responsibilities for marketing, field sales, and customer support to his existing engineering and operations responsibilities, and brought a set of SP&R products onto the Genesis database, the precursor to Open Access database. Since beginning his career at Cadence in 1990, Mr. Brashears has held a variety of field operations and R&D positions.

David Lan Senior Manager, Design Methodology TSMC, N.A.

During Mr. Lan's 9-year service at TSMC, he has been responsible for providing solutions in chip implementation, verification, and DFM to TSMC customers. Prior joining TSMC, he held management positions in various ASIC companies and fabless design companies in CAD, chip integration, and verification area. He received his MS degree in computer engineering from UC Santa Barbara in 1987.

Harold Lehon Vice President and General Manager, RAPID Division KLA-Tencor

Mr. Lehon is responsible for the reticle inspection business, which spans reticle design, manufacturing, and use in the wafer fab. He joined KLA-Tencor in 2001 as vice president of marketing for the RAPID Division. Prior to joining KLA-Tencor, Mr. Lehon was president of DuPont Photomasks Japan KK and vice president of Asia Pacific Sales. Mr. Lehon also served two and half years as an ISAC advisor on international trade in the electronics sector to the U.S. secretary of commerce and the U.S. trade representative.

Riko Radojcic DFM Initiative QUALCOMM CDMA

Dr. Radojcic is a leader of a design-for-SI initiative at QUALCOMM CDMA Technologies. Prior to his current role, he was a consultant providing engineering, business development, marketing, and strategic sales services to semiconductor and EDA companies. He was director of Business Development and Marketing for DFM Solutions at PDF Solutions, Inc., from 2001 to 2004. Prior to PDF, Dr. Radojcic was a business manager and an architect with Tality and Cadence, specializing in design technology integration and process characterization and modeling. He has more than 20 years of experience in the semiconductor industry, specializing in the integration of process and design considerations and DFM solutions.

Sudhakar Sabada Vice President, Customer Design Engineering and Technology LSI Logic

Mr. Sabada is responsible for overseeing LSI's EDA strategy, development of design methodology for cell-based ASIC designs, and engineering aspects of customer design projects in leading-edge process technologies. Prior to this, Mr. Sabada led the development and deployment of the LSI Logic Gflx™ ASIC product based on the 0.11-micron copper low-K process technology. Mr. Sabada has been with LSI Logic since 1989. During this time, Mr. Sabada has held a variety of engineering and engineering management positions in the company.

Atul Sharan President and Chief Executive Officer Clear Shape

Prior to co-founding Clear Shape, Mr. Sharan was vice president of marketing and business development at Synopsys, Inc., leading company DFM strategy and direction after the acquisition of Numerical Technologies. Prior to Synopsys, Mr. Sharan was senior vice president of sales and marketing for Numerical Technologies, Inc., where he was instrumental in establishing key strategic partnerships and growing the business from the pre-revenue stage through its highly successful initial public offering in April 2000 and its eventual acquisition by Synopsys, Inc. Prior to Numerical, Mr. Sharan was in charge of partnerships and business development at Ambit Design Systems (now part of Cadence Design Systems, Inc.).