Fueled by a surge in chip complexity, design, and IP reuse is soaring. While design and IP reuse delivers efficiency, it presents the business and technical challenges of selecting the right IP and integrating it successfully into chip designs. A lack of standards and fragmentation across this area of the supply chain makes it downright difficult for IP integrators to compare, evaluate, and explore a potential IP component in their specific design context. This panel will serve to educate design teams in terms of what strategies IP suppliers are taking to better arm their customers with quality IP, as well as what methods IP integrators are using to explore, evaluate, and ultimately select the IP of choice for their next chip designs.

Kathy Werner President VSI Alliance Reuse Manager Freescale Semiconductor

Ms. Werner has led the industry in its quest for IP standards for many years. She is the president of the VSI Alliance, the leading industry organization for IP standards. She has chaired the VSI Alliance Quality IP Pillar for the past six years; during this time, the first Quality IP (QIP) Metric was introduced. Ms. Werner is also working with the FSA and other industry organizations to extend this metric. As the Freescale Semiconductor Reuse Manager, Ms. Werner is responsible for IP coordination, standardization, and quality, including Freescale's interaction with the Spirit organization, a group that is also involved in SoC and IP issues. Ms. Werner is also the chair for the DesignCon IP Business and Engineering Impacts track.

Robert Barnes Director of Channel Marketing ARM

Mr. Barnes was appointed to director channel marketing in July 2006. He joined ARM in July 2000 as an applications engineer in wireless segment marketing and. Prior to ARM, he held positions at Hitachi Europe as a senior design engineer and sales manager, focusing on development tools support for 16- and 32- bit microprocessors for five years. He holds a bachelor's degree in electrical, electronic, and systems engineering from the University of Coventry in England.

Bob Kirk Director, Strategic Marketing, Structured Digital Products AMI Semiconductor

Mr. Kirk is responsible for the digital products road map at AMI Semiconductor. He has led the development of the XPressArray structured ASIC product line and the company's FPGA/ASIC-to-ASIC conversion service. Mr. Kirk has been with AMIS since 1973, developing CAD/EDA tools, gate array, and standard cell products. In 1981, he established the Twain Harte research center to develop advanced VLSI CAD tools using artificial intelligence techniques.

Walter Ng Senior Director, Platform Alliances Chartered Semiconductor Manufacturing

Mr. Ng is responsible for developing and executing customer and partner alliances that advance the adoption of Chartered's solutions for leading-edge and mainstream technology nodes. He has led the company's collaboration with IBM and Samsung to define the strategy and implementation of solutions for the common design enablement platform at 90 nm, 65 nm, and 45 nm. Previously, he was senior director of design solutions, responsible for Chartered's relationship with third-party EDA and IP partners. Mr. Ng has more than 15 years of experience in the electronic design industry.

Adam Traidman President Chip Estimate Corporation

Prior to joining Chip Estimate, Mr. Traidman ran North America West sales at Hier Design, an FPGA design automation company acquired by Xilinx in 2004. His industry experience includes various management and technical roles at Adaptec, Monterey Design Systems, Texas Instruments, and the NASA JPL. He holds a bachelor's degree in computer and systems engineering from Rensselaer Polytechnic Institute.

Mobashar Yazdani Senior Engineer/Scientist, Global Sourcing and Procurement, Imaging and Printing Hewlett-Packard

Mr. Yazdani is in the R&D lab of HP Product Process organization ASIC program, supporting ASIC development for HP worldwide. Prior to this, he was principal scientist in HP procurement for assessment of silicon providers and managed the ASIC/ASSP technology center in HP supply chain operations for a number of years. He started at HP in 1988 on its first generation of CMOS RISC processors and on various ASICs for the HP enterprise computer line.