Given today's shrinking market windows, multimillion-gate SoCs demand a high degree of design reuse and IP integration from multiple vendors. Issues of interoperability and proving reusability under multiple-use cases represents a considerable design and verification challenge, making IP verification often a more complex task than doing the chip design itself. Most experts agree that there are two fundamental components contributing to the IP verification challenge: interoperability and compliancy. Hear from IP verification experts who will examine the business impact of IP quality and debate how best to tackle these difficult IP verification challenges.

Michael Keating Fellow and Co-Author of the Reuse Methodology Manual Synopsys

Mr. Keating is a Synopsys Fellow in the Advanced Technology Group of Synopsys. He has been with Synopsys for 10 years, focusing on IP development methodology, hardware and software design quality, and low-power design. He received his B.S.E.E. and M.S.E.E. from Stanford University and has more than 20 years of experience in ASIC and system design. He is co-author of the Reuse Methodology Manual.

Craig Cochran Vice President of Marketing Jasper Design Automation

Mr. Cochran is responsible for worldwide marketing and is focused on developing the market for Jasper's innovative products. Prior to joining Jasper, Mr. Cochran was director of Marketing for Synopsys' Galaxy Design Platform, an integrated design implementation platform enabling advanced IC design. Before this, he managed Synopsys' Corporate Marketing group for four years, where he directed outbound marketing and public relations throughout the company's rapid growth to the position of market leader.

Brian Gardner Vice President, IP Products Denali Software

Mr. Gardner oversees the team that designs and markets memory and storage IP platforms. He is a 25-year semiconductor industry veteran. He held senior positions in general management, marketing, and business development at QLogic; OmegaBand, Inc. (an InfiniBand equipment company); and Interactive Silicon (a fabless semiconductor company). Prior to Interactive Silicon, Mr. Gardner spent 18 years at Motorola. As general manager of the microcontroller division, he helped build the 68HC05 microcontroller into a dominant architecture with sales of more than 3 billion units.

Pat Hays Vice President of Engineering MIPS Technologies

Dr. Hays has more than 20 years of semiconductor experience, including engineering management roles at AT&T Bell Laboratories, PictureTel (Polycom), and Lexra, Inc. He co-founded Lexra and served for six years as its chief technology officer, leading the development of its synthesizable 32-bit RISC semiconductor IP. Other career highlights include his work as principal architect of Bell Labs' DSP32, the first DSP with floating-point arithmetic, and his management of Bell Labs' DSP16, for years the world's fastest DSP.

Sherry Xie Manager of Super Mobile and Validation Transmeta Corporation

Ms. Xie is the design manager at Transmeta, where she has led design teams on northbridge, southbridge, and ASIC designs, ranging from design spec definition to tape-out. The designs have covered more than 10 million gates and down to a 65 nm process node. From 1996 to 2000, Ms. Xie was the design leader at Texas Instruments. At TI, she was in charge of multiple USB designs and engaged in 1394 and UART designs. Ms Xie received her B.S. from Tsinghua University in China and her MSEE from Virginia Tech.