Steve Weir, Member Technical Staff, Teraspeed Consulting Group
Scott McMorrow, President, Teraspeed Consulting Group
Al Neves, Member Technical Staff, Teraspeed Consulting Group
Tom Dagostino, Vice President Device Modeling, Teraspeed Consulting Group
Brian Vicich, Engineering Manager Advanced Design Group, Samtec, Inc.

Designing a PCB to obtain minimum SerDes jitter is critical to maximizing high-speed serial-link bandwidth and reliability. The PCB power distribution methodology has a strong impact on SerDes performance. However, optimization for one impairment often comes at the cost of another. Considerable debate remains over which effects dominate and how to reliably yield quality designs. Using carefully designed test vehicles, we characterize Virtex 4 SerDes sensitivity to specific PCB impairments and physical PCB design tradeoffs. We reconcile current debate on best practices and offer a detailed design methodology.