5-WP1
Packaging a Supercomputer in a PCI Express Form Factor
Wednesday, January 31 | 2:00 pm – 2:40 pm
Greg Edlund, Senior Engineer, IBM
When the customer needs a solution that departs from the well-worn path established by design guides, the engineering team needs to make difficult choices regarding reliable operating margins. We will examine the tradeoffs between power, cooling, and performance involved in packaging a multicore microprocessor and associated controller chip on a PCIe card together with large amounts of memory. In particular, we will examine how power and cooling interacted with DC power distribution to more than 20 domains, timing specifications for a DDR2 interface, and PCIe compliance.
