Manoj Roge, System Architect, Altera Corporation
Andy Bellis, Team Lead - Memory Architect Group, Altera Corporation
Joseph Huang, Design Engineering Manager, Altera Corporation
Yan Chong, MTS Design Engineer, Altera Corporation
Phil Clarke, Senior Design Engineer, Altera Corporation

This paper describes the calibration techniques that can maximize the link performance of parallel source synchronous interfaces used by mainstream DRAM and SRAM memories. The focus of memory vendors is to provide lowest-cost memories. Even though memory performances double with every generation, the memory uncertainties do not reduce at the same rate. This puts a significant burden on memory controllers in optimizing the link performance. This paper demonstrates that beyond 800 Mbps, one needs to implement dynamic calibration techniques in order to have sufficient margin over PVT conditions and it can be done with reasonable die size overhead.