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4-TA2
Methodology to Analyze and Insert a Power Mesh Early in the Design Cycle
Tuesday, January 30 | 9:20 am – 10:00 am

Ken Umino, Design Services Consultant, Synopsys
Joseph Schrand, IC Design Engineer, Thomson Silicon Components
Evan Chen, Design Services Consultant, Synopsys

An IC design engineer is often required to perform design-related tasks at the beginning of a project before all necessary data is present. For example, a designer may be asked to explore power-mesh design and analysis before all IP is procured or RTL is complete. The designer may have rough targets for die size, maximum power consumption, and maximum IR drop. Rather than wait, power-mesh design and analysis could be started with this early data. This paper covers a methodology to analyze a power mesh using a dummy net list consisting of only buffers, and then proposes a procedure that inserts a power mesh properly aligned with the routing grid.

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