Thomas Anderson, Product Marketing Manager, Cadence

Three approaches lie at the very heart of modern functional verification-assertions, functional coverage, and constrained-random stimulus generation-all of which are supported by the SystemVerilog language. This talk focuses on the SystemVerilog constructs for specifying assertions and functional coverage points, providing practical guidelines for their effective use. Topics include efficient coding practices, placement of assertions and coverage specifications, relationship to SystemVerilog constraints, and applicability to formal analysis. This talk is appropriate for any design or verification engineer considering use of SystemVerilog, assertions, or functional coverage.