3-TA2
Building Verification IP for Reusability — Based on SystemVerilog and TLM Standards
Tuesday, January 30 | 9:20 am – 10:00 am
Leena Singh, Verification Architect, Rambus Inc.
The complexity of designs calls for sharing in the form of an IP. It is important not only in the design world, but also in the verification world, as the problem is more complex there. This paper addresses how to build a reusable verification IP that epitomizes the protocol domain knowledge and can be packaged up along with the test-bench intelligence in some sharable and executable form. An example verification environment will be discussed based on real verification IPs developed using SystemVerilog, SystemC, and TLM standards. The example is based on the Rambus DDR-based memory system.
