2005 Archive
Highlights | Schedule | Exhibitor List
Schedule view: By Date | By Track
Monday January 31
9:00am – 12:00pm
TF1: Architecture and CAD Software for FPGAs
TF2: Embed Resistors and Capacitors in Circuit Boards Now
TF3: Multi-gigabit Serial Channel Design Methodology - from Architecture, Through Prototype, to Physical Measurement Verification
TF4: Eliminating Unwanted Test Fixture Effects in Multi-Gigabit Device Measurements: Coupled Line S-Parameter Deembedding and Thru-Reflect-Line (TRL) Calibration Technique
TF5: An Introduction to the Electronic System Level (ESL)
TF6: Recent Developments in Signal Integrity Measurement and Analysis
TF2: Embed Resistors and Capacitors in Circuit Boards Now
TF3: Multi-gigabit Serial Channel Design Methodology - from Architecture, Through Prototype, to Physical Measurement Verification
TF4: Eliminating Unwanted Test Fixture Effects in Multi-Gigabit Device Measurements: Coupled Line S-Parameter Deembedding and Thru-Reflect-Line (TRL) Calibration Technique
TF5: An Introduction to the Electronic System Level (ESL)
TF6: Recent Developments in Signal Integrity Measurement and Analysis
12:00pm – 1:00pm
Monday Keynote Luncheon Address
Michael Fister, President & CEO, Cadence Design Systems, Inc.
Michael Fister, President & CEO, Cadence Design Systems, Inc.
1:30pm – 4:30pm
TF7: Inductance of Bypass Capacitors: How to Define, How to Measure, How to Simulate?
TF8: Customized Synthesis for Structured ASICs - Delivering Higher Performance, Quicker Time to Market and Reduced Work on the Back End
TF9: Implementing a Coverage-Driven Constrained-Random Design-for-Verification Methodology with SystemVerilog
TF10: Nanoelectronics TecForum
TF11: Transition to Surface-Mount: An Analysis of Signal Integrity Improvement vs. Manufacturing Concerns in Multi-Gigabit Systems Using High-Density Connectors
TF12: Signal Integrity Techniques for High Speed Serial Link Design
TF8: Customized Synthesis for Structured ASICs - Delivering Higher Performance, Quicker Time to Market and Reduced Work on the Back End
TF9: Implementing a Coverage-Driven Constrained-Random Design-for-Verification Methodology with SystemVerilog
TF10: Nanoelectronics TecForum
TF11: Transition to Surface-Mount: An Analysis of Signal Integrity Improvement vs. Manufacturing Concerns in Multi-Gigabit Systems Using High-Density Connectors
TF12: Signal Integrity Techniques for High Speed Serial Link Design
4:45 pm – 6:00 pm
Conference Panel: Jitter Characterization and Test of Serial Data Designs
Conference Panel: Bypass Capacitors: How to Determine Their Inductance
Conference Panel: Bypass Capacitors: How to Determine Their Inductance
Full-Day Event | 8:30 am - 5:00 pm
Tuesday, February 1
8:30am – 9:10am
A-TA1: Physical Design Methodology for a 0.13um System on a Chip
1-TA1: Implementing High Speed SPI4.2 Interfaces Using FPGAs
3-TA1: Joint Study of Simultaneous Switching Noise and IO Return Current for a CMOS FPGA Package
4-TA1: Development of a 10 Gb I/O connector system
5-TA1: Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems
7-TA1: Test Socket Influence on High Speed Differential Signals and Channel Performance
9-TA1: Automatic Verification of Timing Constraints
10-TA1: The Risks of Shipping Intellectual Property Offshore: What the EDA Industry Should Consider When Outsourcing Offshore
1-TA1: Implementing High Speed SPI4.2 Interfaces Using FPGAs
3-TA1: Joint Study of Simultaneous Switching Noise and IO Return Current for a CMOS FPGA Package
4-TA1: Development of a 10 Gb I/O connector system
5-TA1: Features and Implementation of High-Performance 667Mbs and 800Mbs DDRII Memory Systems
7-TA1: Test Socket Influence on High Speed Differential Signals and Channel Performance
9-TA1: Automatic Verification of Timing Constraints
10-TA1: The Risks of Shipping Intellectual Property Offshore: What the EDA Industry Should Consider When Outsourcing Offshore
9:20am – 10:00am
A-TA2: Implementing High-Speed RLDRAM II Memory Interface with FPGAs
1-TA2: CPU/DSP Combo Chip Handles Embedded Workloads
3-TA2: Z-Axis Power Delivery: Concept and Implementation
4-TA2: Connector Footprint Optimization Enables 10 Gb+ Signal Transmission
5-TA2: Connector-Less Probing - Electrical and Mechanical Advantages
6-TA2: 10Gb/s Receive Equalization for High Loss Backplanes
7-TA2: A Discussion of Rj/Dj Compliance Measurement and What To Do When You Don't Hit Your Numbers
9-TA2: Modeling Data and Transactions in SystemVerilog
10-TA2: Design for Manufacturing: What Designers Need to Know About the Coming Change in Yield Management
1-TA2: CPU/DSP Combo Chip Handles Embedded Workloads
3-TA2: Z-Axis Power Delivery: Concept and Implementation
4-TA2: Connector Footprint Optimization Enables 10 Gb+ Signal Transmission
5-TA2: Connector-Less Probing - Electrical and Mechanical Advantages
6-TA2: 10Gb/s Receive Equalization for High Loss Backplanes
7-TA2: A Discussion of Rj/Dj Compliance Measurement and What To Do When You Don't Hit Your Numbers
9-TA2: Modeling Data and Transactions in SystemVerilog
10-TA2: Design for Manufacturing: What Designers Need to Know About the Coming Change in Yield Management
10:10am – 10:50am
A-TA3: Identifying Sources of Jitter
1-TA3: Soft Error Radiation Test, Simulation and Protection in Nanometer Technologies
2-TA3: An Advanced Methodology for On-chip Passive Component Design and Optimization
3-TA3: 90nm Low Power Implementation of ARM1136JF-S Test Chip
4-TA3: Design of Embedded Capacitors in PCBs and Organic Chip Packages using Ultra-Thin Substrates
5-TA3: 10 Gigabit Channel Virtual Design Kit
6-TA3: The Recessed Probe Launch - A New Signal Launch for High Frequency Characterization of Board Level Packaging
7-TA3: New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links
9-TA3: Maximizing Synergies of Assertions and Coverage Points within a Coverage-Driven Verification Methodology
10-TA3: Outsourcing Designs for Nimble Product Development
1-TA3: Soft Error Radiation Test, Simulation and Protection in Nanometer Technologies
2-TA3: An Advanced Methodology for On-chip Passive Component Design and Optimization
3-TA3: 90nm Low Power Implementation of ARM1136JF-S Test Chip
4-TA3: Design of Embedded Capacitors in PCBs and Organic Chip Packages using Ultra-Thin Substrates
5-TA3: 10 Gigabit Channel Virtual Design Kit
6-TA3: The Recessed Probe Launch - A New Signal Launch for High Frequency Characterization of Board Level Packaging
7-TA3: New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links
9-TA3: Maximizing Synergies of Assertions and Coverage Points within a Coverage-Driven Verification Methodology
10-TA3: Outsourcing Designs for Nimble Product Development
11:00am – 11:40am
A-TA4: Enabling Terabit Backplanes Using Channel Optimization to Reduce the Need for Equalization
1-TA4: Raising the Level of Abstraction for Design and Verification: SystemC and System Verilog in a Multilanguage Environment
2-TA4: "Fearless Partitioning": An Efficient Approach to the Challenges of a True Multi-chip Integration into a Single SOC
3-TA4: Lower Power DRAM: Design Implications and Opportunities
4-TA4: Embedded Passives in Boards and Packages: Case Study on Embedded Resistor Design and Cost Impact
5-TA4: Employing LVDS Chips to Optimize FPGA Interface Performance
6-TA4: Optimized Signal Path for Orthogonal System Architectures
7-TA4: Total Jitter Measurement at Low Probability Levels, using Optimized BERT Scan Method
9-TA4: Bringing Formal Property Verification into the Mainstream
10-TA4: Impact of Diagonal Routing Architecture on Traditional Cost vs. Performance Trade-offs in Digital IC Design
1-TA4: Raising the Level of Abstraction for Design and Verification: SystemC and System Verilog in a Multilanguage Environment
2-TA4: "Fearless Partitioning": An Efficient Approach to the Challenges of a True Multi-chip Integration into a Single SOC
3-TA4: Lower Power DRAM: Design Implications and Opportunities
4-TA4: Embedded Passives in Boards and Packages: Case Study on Embedded Resistor Design and Cost Impact
5-TA4: Employing LVDS Chips to Optimize FPGA Interface Performance
6-TA4: Optimized Signal Path for Orthogonal System Architectures
7-TA4: Total Jitter Measurement at Low Probability Levels, using Optimized BERT Scan Method
9-TA4: Bringing Formal Property Verification into the Mainstream
10-TA4: Impact of Diagonal Routing Architecture on Traditional Cost vs. Performance Trade-offs in Digital IC Design
12:00pm – 12:30pm
Tuesday Keynote Address
Aart de Geus, Chairman and Chief Executive Officer, Synopsys
Aart de Geus, Chairman and Chief Executive Officer, Synopsys
2:00pm – 2:40pm
A-TP1: High-Speed Signaling Design: From 1 Gbps to 10 Gbps
1-TP1: Setting the Standard for Multi-Core SoC Debug and Trace
3-TP1: Integrated Design for IA-64 Microprocessor Power Delivery System
4-TP1: Hybrid Stripline Analysis II: Propagation Characteristics, Crosstalk Effects and PCB Routability
6-TP1: Using Equalization and Crosstalk Cancellation to Enable Next-Generation Throughput Rates on Legacy Backplane Systems
7-TP1: Digital Engineer to Signal Integrity Engineer in 28 Hours
8-TP1: Resolving EMI Problems with Good Power Delivery Strategy
9-TP1: AMBA Compliance Checking Using Static Functional Verification
10-TP1: Your Customers Success is Your Success
IEC Executive Forum: Enabling Innovation on Today's Design Teams
1-TP1: Setting the Standard for Multi-Core SoC Debug and Trace
3-TP1: Integrated Design for IA-64 Microprocessor Power Delivery System
4-TP1: Hybrid Stripline Analysis II: Propagation Characteristics, Crosstalk Effects and PCB Routability
6-TP1: Using Equalization and Crosstalk Cancellation to Enable Next-Generation Throughput Rates on Legacy Backplane Systems
7-TP1: Digital Engineer to Signal Integrity Engineer in 28 Hours
8-TP1: Resolving EMI Problems with Good Power Delivery Strategy
9-TP1: AMBA Compliance Checking Using Static Functional Verification
10-TP1: Your Customers Success is Your Success
IEC Executive Forum: Enabling Innovation on Today's Design Teams
2:50pm – 3:30pm
1-TP2: Designing Practical Bug Free Digital Data Synchronization Circuits across Multiple Clock Domains; including DDR Data Handling.
2-TP2: A Method for Analyzing Full Chip PI and EMI Using Parallel Processed PEEC Model
3-TP2: Low Power Design Methodologies and Optimizations for sub90nm ASIC
4-TP2: The Impact of PCB Laminate Weave on the Electrical Performance of Differential Signaling at Multi-Gigabit Data Rates
6-TP2: Comparison of Adaptive and Non-Adaptive Equalization Techniques in High Performance Backplanes over Temperature, Humidity, and Impedance Variations
7-TP2: Eye Pattern Measurements on Scopes
8-TP2: Modeling and Correlation of Supply Noise for a 3.2GHz Bidirectional Differential Memory Bus
9-TP2: Creating a Provably Correct Design Methodology
10-TP2: A Process for IP Protection
2-TP2: A Method for Analyzing Full Chip PI and EMI Using Parallel Processed PEEC Model
3-TP2: Low Power Design Methodologies and Optimizations for sub90nm ASIC
4-TP2: The Impact of PCB Laminate Weave on the Electrical Performance of Differential Signaling at Multi-Gigabit Data Rates
6-TP2: Comparison of Adaptive and Non-Adaptive Equalization Techniques in High Performance Backplanes over Temperature, Humidity, and Impedance Variations
7-TP2: Eye Pattern Measurements on Scopes
8-TP2: Modeling and Correlation of Supply Noise for a 3.2GHz Bidirectional Differential Memory Bus
9-TP2: Creating a Provably Correct Design Methodology
10-TP2: A Process for IP Protection
3:45 pm – 5:00 pm
IEC Executive Forum: The Power to Innovate: Critical Links in the Design Chain That Can Make or Break a Power-Efficient Design
Conference Panel: ASICs Dive into Mainstream Applications
Conference Panel: Taking the Pain out of Verification: Exploring What has to Change and Why
Conference Panel: Emerging PCB Laminates
Conference Panel: ASICs Dive into Mainstream Applications
Conference Panel: Taking the Pain out of Verification: Exploring What has to Change and Why
Conference Panel: Emerging PCB Laminates
Wednesday, February 2
8:50am – 9:30am
1-WA1: Ultra-Wideband Radio Design for Multi-band OFDM 480 Mb/s Wireless USB
2-WA1: Challenges to Silicon Modeling in the Nanometer Era
5-WA1: Performance Model for Inter-Chip Businesses Considering Bandwidth and Cost
6-WA1: Investigating Microvia Technology for 10Gbps and Higher Telecommunication Systems
7-WA1: Precision Jitter Transmitter
8-WA1: Power Plane Modeling and the Zero Order Mode Approximation
9-WA1: Comparative Discussion of Pre-Silicon Software Validation Alternatives
10-WA1: Towards Automation of IP Reuse Quality Measurement
2-WA1: Challenges to Silicon Modeling in the Nanometer Era
5-WA1: Performance Model for Inter-Chip Businesses Considering Bandwidth and Cost
6-WA1: Investigating Microvia Technology for 10Gbps and Higher Telecommunication Systems
7-WA1: Precision Jitter Transmitter
8-WA1: Power Plane Modeling and the Zero Order Mode Approximation
9-WA1: Comparative Discussion of Pre-Silicon Software Validation Alternatives
10-WA1: Towards Automation of IP Reuse Quality Measurement
9:00am – 10:20am
9:40am – 10:20am
1-WA2: Hard Coded or Simply Software: The Best of Both Worlds in Traffic Management
2-WA2: Three-Dimensional Integrated Circuits Overcome Technical Limitations Inherent to Systems-in-Package
3-WA2: Power and Timing Closures for IC and Package Co-Design
5-WA2: Characterization and Production Test for CEI-6G-LR Compliant 6.25Gbps SerDes
6-WA2: Impact of Manufacturing Parametric Variations on Backplane System Performance
7-WA2: Edge-Optimized Equalization Extends Performance in Multi-Gigabit Serial Signaling
8-WA2: Characterizing and Modeling the Impact of Power/Ground Via Arrays on Power Plane Impedance
9-WA2: Top-Down Post-Layout Mixed-Signal Design Verification Methodology for FPGA-Embedded Multi-Gigabit Transceiver
10-WA2: The Use of Quality Metrics in Effective IP Selection
2-WA2: Three-Dimensional Integrated Circuits Overcome Technical Limitations Inherent to Systems-in-Package
3-WA2: Power and Timing Closures for IC and Package Co-Design
5-WA2: Characterization and Production Test for CEI-6G-LR Compliant 6.25Gbps SerDes
6-WA2: Impact of Manufacturing Parametric Variations on Backplane System Performance
7-WA2: Edge-Optimized Equalization Extends Performance in Multi-Gigabit Serial Signaling
8-WA2: Characterizing and Modeling the Impact of Power/Ground Via Arrays on Power Plane Impedance
9-WA2: Top-Down Post-Layout Mixed-Signal Design Verification Methodology for FPGA-Embedded Multi-Gigabit Transceiver
10-WA2: The Use of Quality Metrics in Effective IP Selection
10:30am – 11:45am
Plenary Panel: Design Verification: From Specification to Closure
Panel Chair: Sergio Camerlo, Director of Engineering, Cisco Systems
Panel Chair: Sergio Camerlo, Director of Engineering, Cisco Systems
12:00pm – 12:30pm
Wednesday Keynote Address
Walden Rhines, Chief Executive Officer and Chairman of the Board of Directors, Mentor Graphics
Walden Rhines, Chief Executive Officer and Chairman of the Board of Directors, Mentor Graphics
2:00pm – 2:40pm
1-WP1: SystemVerilog Implicit Port Connections
3-WP1: Design of a Low-Power Differential Repeater Using Low Voltage Swing and Charge Recycling
5-WP1: Novel Signal and Power Integrity Approaches: High Performance Backplane/Mezzanine Interconnects and Decoupling Interposers
6-WP1: Beyond 10Gbps: Next Generation Serial Interfaces
7-WP1: Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications
8-WP1: Measurements of impedance, current and worst-case noise on chip power delivery system under operating conditions
9-WP1: Design Illumination
IEC Executive Forum: Leadership in Times of Change: Sourcing Skills Differently - Why, What & How
3-WP1: Design of a Low-Power Differential Repeater Using Low Voltage Swing and Charge Recycling
5-WP1: Novel Signal and Power Integrity Approaches: High Performance Backplane/Mezzanine Interconnects and Decoupling Interposers
6-WP1: Beyond 10Gbps: Next Generation Serial Interfaces
7-WP1: Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications
8-WP1: Measurements of impedance, current and worst-case noise on chip power delivery system under operating conditions
9-WP1: Design Illumination
IEC Executive Forum: Leadership in Times of Change: Sourcing Skills Differently - Why, What & How
2:50pm – 3:30pm
1-WP2: Hardware Implementation of a Tree-based IP Lookup Algorithm for OC-768 and Beyond
3-WP2: Co-Design in the PA-8800 Microprocessor
5-WP2: Designing Transceiver FPGA's Using Advanced Calibration Techniques
6-WP2: Novel Time Domain Scaling Technique for Crosstalk Characterization
7-WP2: Addressing the Challenges of Implementing an At-Speed Production Test-Cell for 10Gb/s Wafer Probing
8-WP2: High Performance FPGA Bypass Filter Networks
9-WP2: Deriving Physical Design Understanding Through an Integrated Physical Debug Approach.
3-WP2: Co-Design in the PA-8800 Microprocessor
5-WP2: Designing Transceiver FPGA's Using Advanced Calibration Techniques
6-WP2: Novel Time Domain Scaling Technique for Crosstalk Characterization
7-WP2: Addressing the Challenges of Implementing an At-Speed Production Test-Cell for 10Gb/s Wafer Probing
8-WP2: High Performance FPGA Bypass Filter Networks
9-WP2: Deriving Physical Design Understanding Through an Integrated Physical Debug Approach.
3:45 pm – 5:00 pm
IEC Executive Forum: What is Design for Yield and How Do We get There?
Conference Panel: OpenAccess: Creating State-of-the-Art EDA Tools and Design Flows
Conference Panel: The Trade-Offs of Software Programmability in Video Processors
Conference Panel: Are We Spending Our Verification Resources Wisely?
Conference Panel: OpenAccess: Creating State-of-the-Art EDA Tools and Design Flows
Conference Panel: The Trade-Offs of Software Programmability in Video Processors
Conference Panel: Are We Spending Our Verification Resources Wisely?
Thursday February 3
9:00am – 12:00pm
