2004 Archive
Highlights | Schedule | Exhibitor List
2004 DesignCon Schedule - February 2-5, 2004
Schedule view: By Date | By Track
Monday, February 2
9:00 am – Noon
TF1: Signal Integrity Modeling and Simulation Tools
TF1: Signal Integrity Modeling and Simulation Tools
1:00 pm – 4:00 pm
TF7: A Tutorial on OpenAccess
TF7: A Tutorial on OpenAccess
Tuesday, February 3
9:00 am – 9:45 am
1-TA1: RLDRAM: Features and Applications of the Ubiquitous Low-Latency/High-Bandwidth DRAM
1-TA1: RLDRAM: Features and Applications of the Ubiquitous Low-Latency/High-Bandwidth DRAM
10:00 am – 10:45 am
1-TA2: Abutted Physical Design of a Complex SoC in 0.13u
1-TA2: Abutted Physical Design of a Complex SoC in 0.13u
11:00 am – 11:45 am
1-TA3: Parameterized Global Modeling of Planar Inductors
1-TA3: Parameterized Global Modeling of Planar Inductors
2:00 pm – 2:45 pm
1-TP1: The Necessary Link for Design Closure: LVS-Parasitic Extraction
1-TP1: The Necessary Link for Design Closure: LVS-Parasitic Extraction
Wednesday, February 4
8:30 am – 9:15 am
1-WA1: Front-End RTL Hand-Off Flows, Audits, and Considerations for ASIC Physical Design
1-WA1: Front-End RTL Hand-Off Flows, Audits, and Considerations for ASIC Physical Design
9:30 am – 10:15 am
1-WA2: PCI/PCI-X Interface Design Considerations
1-WA2: PCI/PCI-X Interface Design Considerations
Tuesday, February 3
10:00 am – 10:45 am
2-TA2: Low-Power Design: Don't Forget About the Memory
2-TA2: Low-Power Design: Don't Forget About the Memory
11:00 am – 11:45 am
2-TA3: Multi-Core Embedded Debug for Structured ASIC Systems
2-TA3: Multi-Core Embedded Debug for Structured ASIC Systems
2:00 pm – 2:45 pm
2-TP1: TLM Bus Verification for RTL Compliance
2-TP1: TLM Bus Verification for RTL Compliance
3:00 pm – 3:45 pm
2-TP2: Improving Application Performance with Instruction Set Architecture Extensions to Embedded Processors
2-TP2: Improving Application Performance with Instruction Set Architecture Extensions to Embedded Processors
Wednesday, February 4
8:30 am – 9:15 am
2-WA1: Effective Verilog RTL Coding Guidelines for Coverage/Functional and IP Design
2-WA1: Effective Verilog RTL Coding Guidelines for Coverage/Functional and IP Design
9:30 am – 10:15 am
2-WA2.1: Can IP Quality Be Objectively Measured?
2-WA2.1: Can IP Quality Be Objectively Measured?
9:30 am – 10:15 am
2-WA2.2: High-Performance Java Virtual Machine
2-WA2.2: High-Performance Java Virtual Machine
2:00 pm – 2:45 pm
2-WP1: VHDL-200X and the Future of VHDL
2-WP1: VHDL-200X and the Future of VHDL
3:00 pm – 3:45 pm
2-WP2: System Solutions Based on Multiple, Small, and Optimized DSP Cores Offer the Best of Both Worlds
2-WP2: System Solutions Based on Multiple, Small, and Optimized DSP Cores Offer the Best of Both Worlds
Monday, February 2
9:00 am – Noon
TF2: VHDL Transaction-Based Verification
TF2: VHDL Transaction-Based Verification
Tuesday, February 3
9:00 am – 9:45 am
3-TA1: Emulating/Prototyping a Network Device in a Live Network
3-TA1: Emulating/Prototyping a Network Device in a Live Network
10:00 am – 10:45 am
3-TA2: Verifying a Cryptographic Processor Using a Smart Bus Functional Model
3-TA2: Verifying a Cryptographic Processor Using a Smart Bus Functional Model
11:00 am – 11:45 am
3-TA3: Functional Verification in the Context of Design Reuse
3-TA3: Functional Verification in the Context of Design Reuse
3:00 pm – 3:45 pm
3-TP2: A Custom Hardware/Software Co-Verification Solution for the Design and Development of a High-Speed Digital Oscilloscope Acquisition System
3-TP2: A Custom Hardware/Software Co-Verification Solution for the Design and Development of a High-Speed Digital Oscilloscope Acquisition System
Wednesday, February 4
8:30 am – 9:15 am
3-WA1.1: Overcoming the PCI Express Verification Hurdle
3-WA1.1: Overcoming the PCI Express Verification Hurdle
8:30 am – 9:15 am
3-WA1.2: Bluetooth Transceiver Design with VHDL-AMS
3-WA1.2: Bluetooth Transceiver Design with VHDL-AMS
9:30 am – 10:15 am
3-WA2: What Is the True Cost of Lint?
3-WA2: What Is the True Cost of Lint?
2:00 pm – 2:45 pm
3-WP1: Formal Verification of Block-Level Assertions
3-WP1: Formal Verification of Block-Level Assertions
3:00 pm – 3:45 pm
3-WP2: An Effective Approach to Translate System Models into Hardware Verification Models Using Real-Time Workshop
3-WP2: An Effective Approach to Translate System Models into Hardware Verification Models Using Real-Time Workshop
Thursday, February 5
9:00 am – Noon
TF13: Using PSL/Sugar for Assertion-Based Verification
TF13: Using PSL/Sugar for Assertion-Based Verification
Monday, February 2
1:00 pm – 4:00 pm
TF8: Characterizing Jitter Histograms
TF8: Characterizing Jitter Histograms
Tuesday, February 3
9:00 am – 9:45 am
4-TA1: Testing of High-Speed Serial I/O Interfaces Based on Spectral Jitter Decomposition
4-TA1: Testing of High-Speed Serial I/O Interfaces Based on Spectral Jitter Decomposition
10:00 am – 10:45 am
4-TA2: Statistical and Sensitivity Analysis of Voltage and Timing Budgets of Multi-Gigabit Interconnect Systems
4-TA2: Statistical and Sensitivity Analysis of Voltage and Timing Budgets of Multi-Gigabit Interconnect Systems
11:00 am – 11:45 am
4-TA3: Using Measure-Based Modeling Tools to Extract Backplane Deterministic Jitter
4-TA3: Using Measure-Based Modeling Tools to Extract Backplane Deterministic Jitter
2:00 pm – 2:45 pm
4-TP1: Statistical and System Transfer Function-Based Method for Jitter and Noise in Communication Design and Test
4-TP1: Statistical and System Transfer Function-Based Method for Jitter and Noise in Communication Design and Test
3:00 pm – 3:45 pm
4-TP2: Jitter Separation at Data Rates above 3 Gbps
4-TP2: Jitter Separation at Data Rates above 3 Gbps
Wednesday, February 4
2:00 pm – 2:45 pm
4-WP1: Controlled Eye-Pattern Test and Analysis
4-WP1: Controlled Eye-Pattern Test and Analysis
3:00 pm – 3:45 pm
4-WP2: Use the Right Model for the Simulation of Multi-Gigabit Channels
4-WP2: Use the Right Model for the Simulation of Multi-Gigabit Channels
Thursday, February 5
9:00 am – Noon
TF14: Practical Multi GHz Clocks for ASIC and COT Designs
TF14: Practical Multi GHz Clocks for ASIC and COT Designs
Monday, February 2
9:00 am – Noon
TF3: System Chip Power Integrity and Package Analysis
TF3: System Chip Power Integrity and Package Analysis
1:00 pm – 4:00 pm
TF9: Thin and Very Thin Laminates for Power Distribution Applications: What Is New in 2004?
TF9: Thin and Very Thin Laminates for Power Distribution Applications: What Is New in 2004?
Wednesday, February 4
8:30 am – 9:15 am
5-WA1: Design of the World's Smallest Video Decoder
5-WA1: Design of the World's Smallest Video Decoder
9:30 am – 10:15 am
5-WA2: System-Level Power-Integrity Analysis and Correlation for Multi-Gigabit Designs
5-WA2: System-Level Power-Integrity Analysis and Correlation for Multi-Gigabit Designs
2:00 pm – 2:45 pm
5-WP1: Investigating Via and Discrete Capacitor Effects Using Power-Integrity Design Tool and Measurement Results
5-WP1: Investigating Via and Discrete Capacitor Effects Using Power-Integrity Design Tool and Measurement Results
3:00 pm – 3:45 pm
5-WP2: Modeling Noise on a Printed Circuit Board Power Plane
5-WP2: Modeling Noise on a Printed Circuit Board Power Plane
Monday, February 2
Tuesday, February 3
10:00 am – 10:45 am
6-TA2: Simulation, Design, and Measurements of a High-Performance BGA Package
6-TA2: Simulation, Design, and Measurements of a High-Performance BGA Package
11:00 am – 11:45 am
6-TA3: ASIC Package Characterization and Correlation with Simulation
6-TA3: ASIC Package Characterization and Correlation with Simulation
Monday, February 2
9:00 am – Noon
TF5: Advances in Time and Frequency Domain Measurements, Modeling and Signal Integrity Analysis of Gigabit Interconnects
TF5: Advances in Time and Frequency Domain Measurements, Modeling and Signal Integrity Analysis of Gigabit Interconnects
1:00 pm – 4:00 pm
TF10: Advances in Design, Modeling, Simulation, and Measurement Validation of High-Performance Board-to-Board 5-to-10 Gbps Interconnects
TF10: Advances in Design, Modeling, Simulation, and Measurement Validation of High-Performance Board-to-Board 5-to-10 Gbps Interconnects
Tuesday, February 3
11:00 am – 11:45 am
7-TA3: Tempus-6000: A Signal-Integrity Revolution in Surface Mount Backplane Connectors and SPICE/S-Parameter Extraction Methodology
7-TA3: Tempus-6000: A Signal-Integrity Revolution in Surface Mount Backplane Connectors and SPICE/S-Parameter Extraction Methodology
2:00 pm – 2:45 pm
7-TP1: Obtaining Accurate Device-Only S-Parameter Data to 15-20 GHz Using In-Fixture Measurement Techniques
7-TP1: Obtaining Accurate Device-Only S-Parameter Data to 15-20 GHz Using In-Fixture Measurement Techniques
Wednesday, February 4
8:30 am – 9:15 am
7-WA1: Making S-Parameter Data Suitable for SPICE Modeling
7-WA1: Making S-Parameter Data Suitable for SPICE Modeling
9:30 am – 10:15 am
7-WA2: The Impact of Environmental Conditions on Channel Performance
7-WA2: The Impact of Environmental Conditions on Channel Performance
3:00 pm – 3:45 pm
7-WP2: A Rigorous Approach to High-Speed Interconnect Characterization and Model Correlation through Differential TDR
7-WP2: A Rigorous Approach to High-Speed Interconnect Characterization and Model Correlation through Differential TDR
Thursday, February 5
9:00 am – Noon
TF15: Cray Supercomputer 3.2 Gb/s Serial Interconnect Simulation Using Full-Wave Electromagnetics
TF15: Cray Supercomputer 3.2 Gb/s Serial Interconnect Simulation Using Full-Wave Electromagnetics
Wednesday, February 4
8:30 am – 9:15 am
8-WA1: Method for Optimizing a 10-Gbps PCB Signal Launch
8-WA1: Method for Optimizing a 10-Gbps PCB Signal Launch
2:00 pm – 2:45 pm
8-WP1: Developing a Working Model for Vias
8-WP1: Developing a Working Model for Vias
3:00 pm – 3:45 pm
8-WP2: Modeling and Verification of Backplane Press-Fit PTH Vias
8-WP2: Modeling and Verification of Backplane Press-Fit PTH Vias
Monday, February 2
1:00 pm – 4:00 pm
TF11: Interface Standards for Wireless Networking IC Implementation: Overview, Implementation, Applications
TF11: Interface Standards for Wireless Networking IC Implementation: Overview, Implementation, Applications
Tuesday, February 3
9:00 am – 9:45 am
9-TA1: Instrumentation-Based Analysis of System FPGAs
9-TA1: Instrumentation-Based Analysis of System FPGAs
10:00 am – 10:45 am
9-TA2: Signal Integrity and Timing Analysis Simulation Reuse
9-TA2: Signal Integrity and Timing Analysis Simulation Reuse
11:00 am – 11:45 am
9-TA3: Design of a 3.125-Gbps Interconnect for High-Bandwidth FPGAs
9-TA3: Design of a 3.125-Gbps Interconnect for High-Bandwidth FPGAs
2:00 pm – 2:45 pm
9-TP1: A Primer to the World of Hardware-Dependent Software
9-TP1: A Primer to the World of Hardware-Dependent Software
3:00 pm – 3:45 pm
9-TP2: Using HyperTransport DirectPacket Technology to Simplify Design of Packet-Based Communications Equipment
9-TP2: Using HyperTransport DirectPacket Technology to Simplify Design of Packet-Based Communications Equipment
Tuesday, February 3
9:00 am – 9:45 am
10-TA1: Backplane Differential Channel Microprobe Characterization in Time and Frequency Domains
10-TA1: Backplane Differential Channel Microprobe Characterization in Time and Frequency Domains
10:00 am – 10:45 am
10-TA2: Performance Benefits of Mixed Dielectric Stripline
10-TA2: Performance Benefits of Mixed Dielectric Stripline
11:00 am – 11:45 am
10-TA3: A Hybrid Measurement and Electromagnetic Field Solver Approach for the Design of High-Performance Interconnects: An Investigation of Traces and SMA Transitions
10-TA3: A Hybrid Measurement and Electromagnetic Field Solver Approach for the Design of High-Performance Interconnects: An Investigation of Traces and SMA Transitions
2:00 pm – 2:45 pm
10-TP1: Extending the Life of Today's Backplanes through Simultaneous Bidirectional Transmission
10-TP1: Extending the Life of Today's Backplanes through Simultaneous Bidirectional Transmission
3:00 pm – 3:45 pm
10-TP2: Error-Correction Coding for 10Gb Backplane Transmission
10-TP2: Error-Correction Coding for 10Gb Backplane Transmission
Tuesday, February 3
10:00 am – 10:45 am
11-TA2: A High Channel-Density, Ultra-High Bandwidth Reference Backplane Designed and Manufactured for 10-Gbps NRZ Serial Signaling
11-TA2: A High Channel-Density, Ultra-High Bandwidth Reference Backplane Designed and Manufactured for 10-Gbps NRZ Serial Signaling
11:00 am – 11:45 am
11-TA3: Multi-Mode Memory Controllers for Network DRAM Interfaces
11-TA3: Multi-Mode Memory Controllers for Network DRAM Interfaces
2:00 pm – 2:45 pm
11-TP1: SerDes Architectures and Their Applications
11-TP1: SerDes Architectures and Their Applications
Wednesday, February 4
8:30 am – 9:15 am
11-WA1: Integrating 10G Serial onto a Large Digital CMOS ASSP: Taking 10G from Lab to Production
11-WA1: Integrating 10G Serial onto a Large Digital CMOS ASSP: Taking 10G from Lab to Production
9:30 am – 10:15 am
11-WA2: A Flexible Backplane Serial Link for 5-10Gb Operation in Realistic Environments
11-WA2: A Flexible Backplane Serial Link for 5-10Gb Operation in Realistic Environments
Tuesday, February 3
9:00 am – 9:20 am
RD-TA1.1: A Reference Design for FPGA-Based Linux Applications
RD-TA1.1: A Reference Design for FPGA-Based Linux Applications
9:25 am – 9:45 am
RD-TA1.2: A Reference Design for a JPEG2000 Video Processor
RD-TA1.2: A Reference Design for a JPEG2000 Video Processor
10:00 am – 10:20 am
RD-TA2.1: A Reference Design for an FPGA-Based 64-Bit/133-MHz PCI-X Interface
RD-TA2.1: A Reference Design for an FPGA-Based 64-Bit/133-MHz PCI-X Interface
10:25 am – 10:45 am
RD-TA2.2: A Reference Design for an FPGA-Based 10-Gigabit Ethernet Port
RD-TA2.2: A Reference Design for an FPGA-Based 10-Gigabit Ethernet Port
11:00 am – 11:20 am
RD-TA3.1: A Reference Design for a 3.125-Gigabit Serial Channel Using an FPGA
RD-TA3.1: A Reference Design for a 3.125-Gigabit Serial Channel Using an FPGA
11:25 am – 11:45 am
RD-TA3.2: A Reference Design for Embedded Linux on a Motorola ColdFire Processor
RD-TA3.2: A Reference Design for Embedded Linux on a Motorola ColdFire Processor
Wednesday, February 4
8:30 am – 8:50 am
RD-WA1.1: A Reference Design Platform for FPGA-Based DSP Applications
RD-WA1.1: A Reference Design Platform for FPGA-Based DSP Applications
9:30 am – 9:50 am
RD-WA2.1: A Reference Design Platform for ASICs
RD-WA2.1: A Reference Design Platform for ASICs
9:55 am – 10:15 am
RD-WA2.2: A Reference Design for High-Speed Backplane Designs
RD-WA2.2: A Reference Design for High-Speed Backplane Designs
