DesignCon 2007

Connecting the World of Electronic Design

2004 Archive

Highlights | Schedule | Exhibitor List

2004 DesignCon Schedule - February 2–5, 2004

Schedule view: By Date | By Track

Monday, February 2

8:00 am – 5:00 pm | Co-Located Event

IBIS Users' Group Meeting: Soliciting and Exchanging IBIS Model-Related Information and Ideas

9:00 am – Noon

TF1: Signal Integrity Modeling and Simulation Tools

TF2: VHDL Transaction-Based Verification

TF3: System Chip Power Integrity and Package Analysis

TF4: Package Selection and Design to Meet Custom Thermal Requirements

TF5: Advances in Time and Frequency Domain Measurements, Modeling, and Signal-Integrity Analysis of Gigabit Interconnects

TF6: Introducing the Optical Internetworking Forum Common Electrical I/O Project

Noon – 1:00 pm

TecForum Keynote Luncheon: Jan Rabaey, Professor and Director, Gigascale Silicon Research Center, University of California, Berkeley

1:00 pm – 4:00 pm

TF7: A Tutorial on OpenAccess

TF8: Characterizing Jitter Histograms

TF9: Thin and Very Thin Laminates for Power Distribution Applications: What Is New in 2004?

TF10: Advances in Design, Modeling, Simulation, and Measurement Validation of High-Performance Board-to-Board 5-to-10 Gbps Interconnects

TF11: Wireless Technology Feature: Interface Standards for Wireless Networking IC Implementation: Overview, Implementation, Applications

TF12: Nanotechnology TecForum

2:00 pm – 4:00 pm | Co-Located Event

VSIA Association Meeting: IP Quality in Depth

4:15 pm – 5:30 pm

Conference Panel: OpenAccess Deployment and Adoption

Conference Panel: Serial Design Test and Debug

Tuesday, February 3

9:00 am – 9:45 am

1-TA1: RLDRAM: Features and Applications of the Ubiquitous Low-Latency/High-Bandwidth DRAM

2-TA1: SoC Design Challenges: The Need for System Modeling and IP Integration

3-TA1: Emulating/Prototyping a Network Device in a Live Network

4-TA1: Testing of High-Speed Serial I/O Interfaces Based on Spectral Jitter Decomposition

6-TA1: A 6.4-Gbps SerDes Design in a Low-Cost, High-Density Build-Up Package

9-TA1: Instrumentation-Based Analysis of System FPGAs

10-TA1: Backplane Differential Channel Microprobe Characterization in Time and Frequency Domains

11-TA1: Design of a 6.25-Gbps Backplane SerDes with Top-Down Design Methodology

RD-TA1.1: A Reference Design for FPGA-Based Linux Applications (9:00 am - 9:20 am)

RD-TA1.2: A Reference Design for a JPEG2000 Video Processor (9:25 am - 9:45 am)

10:00 am – 10:45 am

1-TA2: IOM Gate SoC Implementation

2-TA2: Low-Power Design: Don't Forget About the Memory

3-TA2: Verifying a Cryptographic Processor Using a Smart Bus Functional Model

4-TA2: Statistical and Sensitivity Analysis of Voltage and Timing Budgets of Multi-Gigabit Interconnect Systems

6-TA2: Simulation, Design, and Measurements of a High-Performance BGA Package

9-TA2: Signal Integrity and Timing Analysis Simulation Re-Use

10-TA2: Potential Benefits of Mixed Dielectric Stripline

11-TA2: A High Channel-Density, Ultra-High Bandwidth Reference Backplane Designed and Manufactured for 10-Gbps NRZ Serial Signaling

RD-TA2.1: A Reference Design for an FPGA-Based 64-Bit/133MHz PCI-X Interface (10:00 am - 10:20 am)

RD-TA2.2: A Reference Design for an FPGA-Based 10 Gigabit Ethernet Port (10:25 am - 10:45 am)

11:00 am – 11:45 am

1-TA3: Parameterised Global Modeling of Planar Inductor

2-TA3: Multi-Core Embedded Debug for Structured ASIC Systems

3-TA3: Functional Verification in the Context of Design Reuse

4-TA3: Using Measure-Based Modeling to Extract Backplane Deterministic Jitter

6-TA3: ASIC Package Characterization and Correlation with Simulation

7-TA3: Tempus-6000: A Signal-Integrity Revolution in Surface Mount Backplane Connectors and SPICE/S-Parameter Extraction Methodology

9-TA3: Design of 3.125-Gbps Interconnects for High-Bandwidth FPGAs

10-TA3: A Hybrid Measurement and Electromagnetic Field Solver Approach for the Design of High-Performance Interconnects: An Investigation of Traces and SMA Transitions

11-TA3: Multi-Mode Memory Controllers for Network DRAM Interfaces

RD-TA3.1: A Reference Design for a 3.125-Gigabit Serial Channel Using an FPGA (11:00 am - 11:20 am)

RD-TA3.2: A Reference Design for Embedded Linux on a Motorola ColdFire Processor (11:25 am - 11:45 am)

Noon – 12:30 pm

Keynote Address: Aart de Geus, Chairman and Chief Executive Officer, Synopsys

12:30 pm – 2:00 pm

Lunch and Technology Exhibition

2:00 pm – 2:45 pm

1-TP1: The Necessary Link for Design Closure: LVS-Parasitic Extraction

2-TP1: TLM Bus Verification for RTL Compliance

3-TP1: On-Chip HDTV Test Pattern Generators Enhance System and Device Testing

4-TP1: Statistical and System Transfer Function Based Method for Jitter and Noise in Communication Design and Test

6-TP1: Package and Test Environment Design for a 10 Gigabit Ethernet Transceiver

7-TP1: Obtaining Accurate Device-Only S-Parameter Data to 15-20 GHz Using In-Fixture Measurement Techniques

9-TP1: A Primer to the World of Hardware-Dependent Software

10-TP1: Extending the Life of Today's Backplanes through Simultaneous Bidirectional Transmission

11-TP1: SerDes Architectures and Applications

3:00 pm – 3:45 pm

1-TP2: Breaking Down the Barriers of IC Integration with 3D Semiconductors

2-TP2: Improving Application Performance with Instruction Set Architecture Extensions to Embedded Processors

3-TP2: A Custom Hardware/Software Co-Verification Solution for the Design and Development of a High-Speed Digital Oscilloscope Acquisition System

4-TP2: Jitter Separation at Data Rates above 3 Gbps

6-TP2: Enhancing the Performance of Wirebonded Organic BGA Packages Through Package Co-Design: A Case Study of a 12.5 Gbit/sec 16:1 Multiplexer with Clock Generator

7-TP2: Utilizing TDRs and VNAs to Develop Four-Port Frequency-Dependent Models

9-TP2: Using HyperTransport DirectPacket Technology to Simplify Design of Packet-Based Communications Equipment

10-TP2: Error-Correction Coding for 10-Gb Backplane Transmission

11-TP2: Wireless Technology Feature: End-to-End Digital Interconnect for 802.11 WLAN Sub-System Implementation

4:00 pm – 5:15 pm

Conference Panel: Establishing Pass-Fail Criteria for High-Speed Digital Interfaces

Conference Panel: Solving the Real Challenges of Low-Power SoC Design in 90 Nanometers

Conference Panel: Wireless Technology Feature: Wireless Design Challenges

5:15 pm – 6:30 pm

Reception on Exhibits Floor

Wednesday, February 4

8:30 am – 9:15 am

1-WA1: Front-End RTL Hand-Off Flows, Audits, and Considerations for ASIC Physical Design

2-WA1: Effective Verilog RTL Coding Guidelines for "Coding for Coverage"

3-WA1.1: Overcoming the Verification Hurdle for PCI Express

3-WA1.2: Bluetooth Transceiver Design with VHDL-AMS

5-WA1: Design of the World's Smallest Video Decoder

7-WA1: Making S-Parameter Data Suitable for SPICE Modeling

8-WA1: Method for Optimizing a 10-Gbps PCB Signal Launch

11-WA1: Integrating 10G Serial onto a Large Digital CMOS ASSP: Taking 10G from Lab to Production

RD-WA1.1: A Reference Design Platform for FPGA-Based DSP Applications (8:30 am - 8:50 am)

RD-WA1.2: A Reference Design Platform for Processor-Based DSP Applications (8:55 am - 9:15 am)

9:00 am – 10:15 am

IEC Executive Forum: FPGA vs. ASIC Design

9:30 am – 10:15 am

1-WA2: PCI/PCI-X Interface Design Considerations

2-WA2.1: Can IP Quality Be Objectively Measured?

2-WA2.2: High-Performance Java Virtual Machine

3-WA2: What Is the True Cost of Lint?

5-WA2: System-Level Power-Integrity Analysis and Correlation for Multi-Gigabit Designs

7-WA2: The Impact of Environmental Conditions on Channel Performance

8-WA2: Crosstalk in 10-Gbps Serial Channels: Optimizing the Forgotten Component

11-WA2: A Flexible Backplane Serial Link for 5-10Gb in Realistic Environments

RD-WA2.1: A Reference Design Platform for ASICs (9:30 am - 9:50 am)

RD-WA2.2: A Reference Design for High-Speed Backplane Designs (9:55 am - 10:15 am)

10:30 am – Noon

Plenary Panel: The Roadmap to 65 Nanometers: Design Needs and Technical Challenges

Noon – 12:30 pm

Keynote Address: Tsugio Makimoto, Corporate Advisor, Semiconductor Operations, Sony

12:30 pm – 2:00 pm

Lunch and Technology Exhibition

2:00 pm – 2:45 pm

1-WP1: Case Studies on Improving FPGA Performance Using Physical Synthesis

2-WP1: VHDL-200X and the Future of VHDL

3-WP1: Formal Verification of Block-Level Assertions

4-WP1: Controlled Eye-Pattern Test and Analysis

5-WP1: Investigating Via and Discrete Capacitor Effects Using Power-Integrity Design Tool and Measurement Results

7-WP1: Channel Compliance Testing Utilizing Novel Statistical Eye Methodology

8-WP1: Developing a Working Model for Vias

2:30 pm – 3:45

IEC Executive Forum: EDA Licensing Models

3:00 pm – 3:45 pm

1-WP2: Full-Chip Signal and Power Integrity with Silicon Substrate Effect

2-WP2: System Solutions Based on Multiple, Small, and Optimized DSP Cores Offer the Best of Both Worlds

3-WP2: An Effective Approach to Translate System Models into Hardware Verification Models Using Real-Time Workshop

4-WP2: Use the Right Model for the Simulation of Multi-Gigabit Channels

5-WP2: Modeling Noise on a Printed Circuit Board Power Plane

7-WP2: A Rigorous Approach to High-Speed Interconnect Characterization and Model Correlation through Differential TDR

8-WP2: Modeling and Verification of Backplane Press-Fit PTH Vias

4:00 pm – 5:15 pm

IEC Executive Forum: Leadership in Times of Change

Conference Panel: Board and Package Level PDN Simulations

Conference Panel: Acceptance of Next-Generation Verification Methods: Roadblocks and Enablers

5:15 pm – 6:30 pm

Reception on Exhibits Floor

Thursday, February 5

9:00 am – noon

TF13: Assertion-Based Verification With Psl: Paradigm Shift In Design Process

TF14: Practical Multi-GHz Clocks for ASIC and COT Designs

TF15: Cray Supercomputer 3.2-Gbps Serial Interconnect Simulation Using Full-Wave Electromagnetics

TF16: Reconfigurable Systems: Introduction to Adaptive Computing

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