Highlights | Schedule | Exhibitor List

Much has been written about the strong benefits attached to learning and using the newest formal and semi-formal circuit verification methods in the ASIC and SoC design flow (meaning assertions, temporal and protocol checking, functional coverage items and other). However, to this point relatively few design teams have accepted much (if any) of these recommendations. The question before the panelists therefore is: "Why is it like that, and what can be done to increase acceptance?" Panelists will discuss experiences, tools or other issues that may have inhibited acceptance and implementation of these methods (especially by the engineers and teams "in the trenches"), and suggestions or ideas about greasing the skids and smoothing the way toward getting them accepted and used.

Chairperson

Gary Smith, Chief Analyst, Gartner Dataquest, was a consultant in design methodology before joining Gartner. Prior to that, he was at LSI Logic, where he became involved in the development of the RT level design methodology. Starting in the semiconductor industry, Mr. Smith was involved in some of the first attempts at customer-designed ICs. He is a current member of the design TWG for the International Semiconductor Road Map (ITRS).

Panelists

Michael Armstrong, ASIC Design Verification Engineer, Texas Instruments, is currently a verification lead for the DLP(tm) Products ASIC development team at Texas Instruments is focused on methodology improvements involving the strategic link between specific verification requirements and their functional coverage measurements, and the integration of industry standard tools into the verification simulation environment. Michael Armstrong's background is in ASIC architecture, design and verification.

Brian Bailey, Chief Technologist, Mentor Graphics, is responsible for setting the technology direction for the group. Previously, Bailey was involved in the creation of the Mentor Graphics Seamless Co-Verification Environment for hardware and software co-simulation. Prior to his work with the Seamless product, Bailey worked with a variety of simulation technologies, including simulation acceleration, emulation, mixed-signal and multi-level simulators. Bailey began his career in the aircraft design business before leaving to work on the emergence of RTL simulation.

Guy Bois, Professor, Electrical Engineering, Ecole Polytechnique de Montreal, has in the last year completed an industrial sabbatical with STMicroelectronics. His research interests include hardware/software co-design and co-verification for embedded systems. Mr. Bois received B.Sc. (1985) and Ph.D. (1990) degrees in computer science from the University of Montreal and has been in his current role since 1991.

Harry Foster, Chief Methodologist, Jasper Design Automation, serves as chairman of the Accellera Formal Verification Technical Committee, which is currently defining the PSL property specification language standard. Prior to joining Jasper Design Automation, Mr. Foster was Verplex Systems' chief architect. He has researched and developed formal verification tools and methodologies for over 12 years as a senior member of the CAD technical staff at Hewlett-Packard, and is the original creator of the Accellera Open Verification Library (OVL) assertion monitor standard.

David Whipp, Verification Architect, NVIDIA, has worked in Europe and the United States doing verification at a range of scales-from microcell libraries, through macrocells and procesor cores, to SoC and complex ASICs. He has presented a number of papers focusing on the modeling aspect of verification, including a transaction modeling paper at last year's DesignCon.