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6-TA1
Tuesday, February 3 | 9:00 am - 9:50 am
A 6.4 Gb/s SerDes Design in a Low-Cost, High-Density Build-Up Package
Kevin Roselle, Chief Technology Officer, Bayside Design
C. Thomas Gray, Senior Staff Design Engineer, Cadence Design Systems
Daniel Lambalot, Member of the Technical Staff, Bayside Design
Jason Oversmith, Member of the Technical Staff, Bayside Design
Jason Thurston, Senior Design Engineer, Cadence Design Systems
Terry Perkinson, Services Project Manager, Cadence Design Systems

Today's semiconductor manufacturers are presented with a serious dilemma: How are semiconductor companies to manufacture very-high-performance chips generally requiring higher cost substrates to satisfy performance demands yet still have a product that is cost-competitive in a market with razor thin margins? This paper addresses one promising solution to that dilemma. A popular package type being used in industry today is the high-density build-up (HDBU) substrate. The technology is basically very fine resolution PCB technology using an organic PCB-like material for the build-up and core layers (BT or similar resin) and thin copper metallization. Several simulation results are shown contrasting the response of a standard HDBU interface with the optimized design described.

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