A new method for verifying the jitter performance of high-speed serial I/O interfaces embedded into SoC devices such as PCI Express, Hypertransport, Serial ATA, XAUI, and SONET is proposed in this paper. The originality of the method is that jitter-normally a time domain parameter-is expressed in its frequency components. Unique to this method is the use of equipment for the classical BER test, and the method can also be applied on ATE systems. This paper describes the Spectral Jitter Decomposition Method with an overview of the basic approach and mathematical modeling, sharing some practical results.