2003 Archive
Highlights | Schedule | Exhibitor List
2003 DesignCon Schedule
January 27–30, 2003
Monday, January 27
9:00 am – Noon
SA-TF1
On Design and Analysis of Complex Programmable Systems
On Design and Analysis of Complex Programmable Systems
SA-TF2
The Power of SystemVerilog
The Power of SystemVerilog
SA-TF3
Verification Technologies
Verification Technologies
HP-TF1
An Overview of Signal Integrity
An Overview of Signal Integrity
HP-TF2
Measurement of Power-Distribution Networks and Their Elements
Measurement of Power-Distribution Networks and Their Elements
NANO TF
NanoEngineering TecForum
NanoEngineering TecForum
Noon – 1:00 pm
TecForum Luncheon
1:00 pm – 4:00 pm
SA-TF3
Verification Technologies
Verification Technologies
SA-TF4
HyperTransport I/O Link Adds Networking Extensions for Next-Generation Communications Design
HyperTransport I/O Link Adds Networking Extensions for Next-Generation Communications Design
SA-TF5
SoC Challenges: Signal Design and Integrity
SoC Challenges: Signal Design and Integrity
HP-TF3
Measurement-Based Signal-Integrity Analysis of Gigabit Interconnect Links
Measurement-Based Signal-Integrity Analysis of Gigabit Interconnect Links
HP-TF4
I2C Bus Overview
I2C Bus Overview
NANO TF
NanoEngineering TecForum
NanoEngineering TecForum
Tuesday, January 28
9:00 am – 9:25 am
RD-1
A Reference Design for a USB 2.0 to SCSI Peripheral
A Reference Design for a USB 2.0 to SCSI Peripheral
9:25 am – 9:50 am
RD-2
A Reference Design for a Rapid I/O End Point USing a Motorola 857T Processor and a Xilinx FPGA-Based IP Core
A Reference Design for a Rapid I/O End Point USing a Motorola 857T Processor and a Xilinx FPGA-Based IP Core
9:00 am – 9:50 am
SA1-1
Field Programmable System-on-Chip for Ethernet/SONET
Field Programmable System-on-Chip for Ethernet/SONET
SA2-1
Scalable Physical Design Implementation in the World of Nanometer Process Technology
Scalable Physical Design Implementation in the World of Nanometer Process Technology
SA5-1
A Practical Approach to Preventing Simultaneous Switching and Ground Bounce Problems in I/O Rings
A Practical Approach to Preventing Simultaneous Switching and Ground Bounce Problems in I/O Rings
HP1-1
DDR2 SDRAM Technology: Device Trends, Functionality, and a Signal-Integrity Case Study
DDR2 SDRAM Technology: Device Trends, Functionality, and a Signal-Integrity Case Study
HP2-1
Late-Breaking News on Bold New Limits for Ultra-High Data Rates on Copper
Late-Breaking News on Bold New Limits for Ultra-High Data Rates on Copper
HP5-1
BER Link Simulations at 10 Gbps
BER Link Simulations at 10 Gbps
10:00 am – 10:25 am
RD-3
A Reference Design for 200 MHz RLDRAM Memory Controller in a Xilinx FPGA
A Reference Design for 200 MHz RLDRAM Memory Controller in a Xilinx FPGA
10:25 am – 10:50 am
RD-4
A Reference Design for a 10/100/1000BaseT Ethernet Connection using an FPGA and External PHY
A Reference Design for a 10/100/1000BaseT Ethernet Connection using an FPGA and External PHY
10:00 am – 10:50 am
SA2-2
Directed Dynamic Simulation Methods for Nanometer Processes
Directed Dynamic Simulation Methods for Nanometer Processes
SA3-1
Experiences with RTL–Synchronized Transaction Reference Models
Experiences with RTL–Synchronized Transaction Reference Models
SA5-2
Impact of Various Source Jitter Components on Equalized Link Performance
Impact of Various Source Jitter Components on Equalized Link Performance
HP1-2
Designing for Multiprotocol SERDES: SFI, NPSI, and SPI-4
Designing for Multiprotocol SERDES: SFI, NPSI, and SPI-4
HP2-2
A Chip-to-Chip Approach to Designing Equalization and Signal Conditioning for High-Performance Networks
A Chip-to-Chip Approach to Designing Equalization and Signal Conditioning for High-Performance Networks
HP3-1
New IBIS Modeling Approaches for Internal Terminated LVDS Buffers
New IBIS Modeling Approaches for Internal Terminated LVDS Buffers
HP5-2
Anatomy of a Signal-Integrity Failure
Anatomy of a Signal-Integrity Failure
10:30 am – 11:30 am
"How to Work with EDN" - A one-hour writing seminar for editorial contributors
11:00 am – 11:25 am
RD-5
A Reference Design for a High-Speed Video Surveillance System
A Reference Design for a High-Speed Video Surveillance System
11:25 am – 11:50 am
RD-6
A New Reference Design Development Environment for JPEG2000 Applications
A New Reference Design Development Environment for JPEG2000 Applications
11:00 am - 11:50 am
SA1-3
Solving the Flash Latency Gap with Multi-Thread CPU Architecture in Embedded Design
Solving the Flash Latency Gap with Multi-Thread CPU Architecture in Embedded Design
SA2-3
A Combined Hardware-Software Approach for Low-Power SoCs: Applying Adaptive Voltage Scaling and the Vertigo Performance-Setting Algorithms
A Combined Hardware-Software Approach for Low-Power SoCs: Applying Adaptive Voltage Scaling and the Vertigo Performance-Setting Algorithms
SA3-2
Co-Simulation Between SystemC and a New Generation of Emulation Platform
Co-Simulation Between SystemC and a New Generation of Emulation Platform
SA5-3
Clock Distribution and Balance in a Large and Complex ASIC: Issues and Solutions
Clock Distribution and Balance in a Large and Complex ASIC: Issues and Solutions
HP1-3
Maximizing 10-Gbps Transmission Path Length in Copper Backplanes with and without Transceiver Technology
Maximizing 10-Gbps Transmission Path Length in Copper Backplanes with and without Transceiver Technology
HP2-3
Enhancements of Copper Transmission Lines for Digital Data Rates Greater Than 2.5 Gpbs
Enhancements of Copper Transmission Lines for Digital Data Rates Greater Than 2.5 Gpbs
HP3-2
Coupled Transmission Line Modeling Alternates and Their Comparisons
Coupled Transmission Line Modeling Alternates and Their Comparisons
HP5-3
Pad Capacitance Extraction Methodology for IBIS Modeling
Pad Capacitance Extraction Methodology for IBIS Modeling
Noon – 1:00 pm
Keynote Luncheon
2:00 pm - 2:50 pm
SA1-4
Creating a High-Performance Reusable 10-Gigabit Ethernet MAC Design
Creating a High-Performance Reusable 10-Gigabit Ethernet MAC Design
SA2-4
An Application of Crosstalk Prevention and Analysis to the Design of a Deep Submicron ASIC
An Application of Crosstalk Prevention and Analysis to the Design of a Deep Submicron ASIC
SA3-4
Installing Functional Coverage Metrics into VHDL Verification Simulations
Installing Functional Coverage Metrics into VHDL Verification Simulations
SA5-4
Asynchronous Logic: Solving Today's Issues, Slaying the Synchronous Design Demon
Asynchronous Logic: Solving Today's Issues, Slaying the Synchronous Design Demon
HP1-4
How to Make Optimal Use of Signal Conditioning in 40-Gbps Copper Interconnects
How to Make Optimal Use of Signal Conditioning in 40-Gbps Copper Interconnects
HP2-4
New Backplane Connector Technology for 10-Gbps Applications
New Backplane Connector Technology for 10-Gbps Applications
HP3-4
Design and Simulation of a RDRAM Channel with 32-Bit 5.33-GB/s Memory Modules
Design and Simulation of a RDRAM Channel with 32-Bit 5.33-GB/s Memory Modules
HP5-4
Noise Allocation for Near-End Crosstalk and Uncertainty in Characteristic Impedance
Noise Allocation for Near-End Crosstalk and Uncertainty in Characteristic Impedance
3:00 pm - 3:50 pm
SA1-5
A Programmable System with Quick Reconfiguration
A Programmable System with Quick Reconfiguration
SA2-5
Increasing the Quality of Embedded Memory
Increasing the Quality of Embedded Memory
SA3-5
Accelerating Verification through Pre-Use of System-Level Test-Bench Components
Accelerating Verification through Pre-Use of System-Level Test-Bench Components
HP1-5
Understanding the Changing World of Backplanes
Understanding the Changing World of Backplanes
HP2-5
Designing a Simple, Small, Wideband, and Low-Power Equalizer for FR4 Copper Links
Designing a Simple, Small, Wideband, and Low-Power Equalizer for FR4 Copper Links
HP3-5
Logic Analyzer Probing Techniques for High-Speed Digital Systems
Logic Analyzer Probing Techniques for High-Speed Digital Systems
HP5-5
Does Signal-Integrity Engineering Have a Future?
Does Signal-Integrity Engineering Have a Future?
4:00 pm – 5:15 pm
SA Panel
Can Anyone Really Afford to Test a Complex SoC?
Can Anyone Really Afford to Test a Complex SoC?
HP Panel
Advances in Active Signal Conditioning Technologies
Advances in Active Signal Conditioning Technologies
Wednesday, January 29
8:30 am – 8:55 am
RD-7
Designing a 3DES Security Micro-Controller for FPGA/ASIC
Designing a 3DES Security Micro-Controller for FPGA/ASIC
8:55 am – 9:20 am
RD-8
A Reference Design Platform for an Embedded Processor in an FPGA using Xilinx MicroBlaze IP Core
A Reference Design Platform for an Embedded Processor in an FPGA using Xilinx MicroBlaze IP Core
8:30 am – 9:20 am
SA2-6
Encryption Instructions Mapped on a Configurable RISC Processor
Encryption Instructions Mapped on a Configurable RISC Processor
HP1-6
The High-Speed Backplane Initiative: An Overview of the Specification and the Technical Challenges It Faces
The High-Speed Backplane Initiative: An Overview of the Specification and the Technical Challenges It Faces
HP1-7
Migrating to New IC Package Designs and Their Effects on Signal Integrity
Migrating to New IC Package Designs and Their Effects on Signal Integrity
HP2-6
Connector and Chip Vendors Come Together to Produce a High-Performance 10-Gbps NRZ Capable Serial Backplane
Connector and Chip Vendors Come Together to Produce a High-Performance 10-Gbps NRZ Capable Serial Backplane
HP3-6
Signal-Integrity Measurements Support the Candidacy of PTFE at High Data Rates
Signal-Integrity Measurements Support the Candidacy of PTFE at High Data Rates
HP4-1
Equalization: Design of Passive Equalizers for Infiniband Cables
Equalization: Design of Passive Equalizers for Infiniband Cables
9:30 am – 9:55 am
RD-9
A Reference Design for Embedded Internet Connectivity
A Reference Design for Embedded Internet Connectivity
RD-11
Video-Processing Reference Design Demonstrates Platform-Independent Design Methodology for FPGAs
Video-Processing Reference Design Demonstrates Platform-Independent Design Methodology for FPGAs
9:55 am – 10:20 am
RD-10
A High–Speed Switch Reference Design Using a Xilinx Vertex–11Pro FPGA Reference Design Platform
A High–Speed Switch Reference Design Using a Xilinx Vertex–11Pro FPGA Reference Design Platform
9:30 am – 10:20 am
SA3-6
A Unified Functional Verification Approach for Mixed Analog-Digital ASIC Designs
A Unified Functional Verification Approach for Mixed Analog-Digital ASIC Designs
SA4-1
Identifying Design-for-Testability Violations in RTL Designs
Identifying Design-for-Testability Violations in RTL Designs
HP1-8
Eye-Opening Techniques Enabled Dispersion Compensation
Eye-Opening Techniques Enabled Dispersion Compensation
HP1-9
Physical-Layer Design and Characterization of a 3.2-Gbps/Pair Memory Channel
Physical-Layer Design and Characterization of a 3.2-Gbps/Pair Memory Channel
HP2-7
Characterizing Jitter Performance of High-Speed Digital Devices Using Innovative Sampling Technology
Characterizing Jitter Performance of High-Speed Digital Devices Using Innovative Sampling Technology
HP3-7
Developing a Specification for 10-Gbps Electrical Transmission in Copper
Developing a Specification for 10-Gbps Electrical Transmission in Copper
HP4-2
Applications of the New Variance-Based PLL Analysis and Measurement Method
Applications of the New Variance-Based PLL Analysis and Measurement Method
10:30 am – Noon
Plenary Panel:
Challenges at 90 Nanometers
Challenges at 90 Nanometers
Noon – 1:00 pm
Keynote Luncheon
2:00 pm – 2:50 pm
SA3-7
Assertion-Based Parameter Checking for IP
Assertion-Based Parameter Checking for IP
SA4-2
Using VTOC for Large SoC Concurrent Engineering: A Real-World Case Study
Using VTOC for Large SoC Concurrent Engineering: A Real-World Case Study
HP1-10
The 1V CMOS 10-Gbps Current Mode Bidirectional Signaling Link with Equalization
The 1V CMOS 10-Gbps Current Mode Bidirectional Signaling Link with Equalization
HP1-11
Automated Model Extraction for Gigabit EDA Library Development
Automated Model Extraction for Gigabit EDA Library Development
HP2-8
Performance Specification of Interconnects
Performance Specification of Interconnects
HP3-8
Characterization of Serial ATA Interconnection at Gigabit Speeds
Characterization of Serial ATA Interconnection at Gigabit Speeds
HP3-9
How to Apply SERDES Performance to Your Design
How to Apply SERDES Performance to Your Design
HP4-3
Beyond DDR: Signal Integrity and Timing Analysis of QBM Systems
Beyond DDR: Signal Integrity and Timing Analysis of QBM Systems
3:00 pm – 3:50 pm
SA4-3
Maximizing Power Delivery at Test and Building a Non-Uniform Sort Test Interface
Maximizing Power Delivery at Test and Building a Non-Uniform Sort Test Interface
HP1-12
High–Speed Design Challenges for a 1.4-GHz Network Processor
High–Speed Design Challenges for a 1.4-GHz Network Processor
HP2-10
Active Cable Assemblies for 10-Gigabit Ethernet
Active Cable Assemblies for 10-Gigabit Ethernet
HP2-11
Practical Guidelines for the Implementation of Backdrilling Vias in Multi-Gigabit Board Applications
Practical Guidelines for the Implementation of Backdrilling Vias in Multi-Gigabit Board Applications
HP3-10
Decomposition of Coplanar and Multilayer Interconnect Structures with Split Power-Distribution Planes for Hybrid Circuit Field Analysis
Decomposition of Coplanar and Multilayer Interconnect Structures with Split Power-Distribution Planes for Hybrid Circuit Field Analysis
HP3-11
Design, Modeling, and Characterization of High-Speed Backplane Interconnects
Design, Modeling, and Characterization of High-Speed Backplane Interconnects
HP4-4
How Accurate Are Your Jitter Measurements?
How Accurate Are Your Jitter Measurements?
4:00 pm – 5:15 pm
SA Panel:
Intellectual Property Cores — A Report from the Trenches
Intellectual Property Cores — A Report from the Trenches
HP Panel:
Challenges in Designing/Verifying a 2.5 to 3.2 Gbps Time-Domain Transmission System
Challenges in Designing/Verifying a 2.5 to 3.2 Gbps Time-Domain Transmission System
IEC Executive Forum:
Leadership in Times of Change — Keeping the Engineering Team's Skills and Tools Up to Date
Leadership in Times of Change — Keeping the Engineering Team's Skills and Tools Up to Date
Thursday, January 30
9:00 am – Noon
SA-TF6
Pre-Silicon Prototypes: An Essential Element in SoC Development
Pre-Silicon Prototypes: An Essential Element in SoC Development
SA-TF7
Advanced Avoidance of Analysis of Signal-Integrity Issues: A Real Project Experience
Advanced Avoidance of Analysis of Signal-Integrity Issues: A Real Project Experience
HP-TF5
PCI Express Architecture and Implementation Considerations
PCI Express Architecture and Implementation Considerations
HP-TF6
Making Precision High-Speed Digital Measurements
Making Precision High-Speed Digital Measurements
