2002 Archive
Highlights | Schedule | Exhibitor List
2002 DesignCon Schedule
January 28–31, 2002
Monday, January 28, 2002
9:00 am – Noon
TecForums
Noon – 1:00 pm
TecForum Luncheon
1:00 pm – 4:00 pm
TecForums
4:00 pm – 6:00 pm
VSIA Forum Addresses SoC Reuse Issues
Tuesday, January 29, 2002
9:00 am – 11:50 am
Conference Sessions
9:00 am – 11:30 am
IEC Executive Forum:
Leadership in Times of Change: Managing the Engineering Process in Times of Disruptive Market Shifts and Challenges
Leadership in Times of Change: Managing the Engineering Process in Times of Disruptive Market Shifts and Challenges
Noon – 1:00 pm
Luncheon Keynote Presentation:
Ray Bingham, President and Chief Executive Officer, Cadence Design Systems
Ray Bingham, President and Chief Executive Officer, Cadence Design Systems
12:30 pm – 6:30 pm
Exhibits Open
2:00 pm – 4:50 pm
Conference Sessions
4:00 pm – 5:15 pm
System-on-Chip and IP Design Conference Panel:
Platform-Based Design: Breakthrough or Pipedream?
Platform-Based Design: Breakthrough or Pipedream?
4:00 pm – 5:15 pm
High-Performance System Design Conference Panel:
Switch Fabric Interface (SFI) versus Good Old Parallel Backplanes: A Time and Place for Each
Switch Fabric Interface (SFI) versus Good Old Parallel Backplanes: A Time and Place for Each
4:45 pm – 6:30 pm
Evening Reception on Exhibits Floor
Wednesday, January 30, 2002
8:30 am – 10:00 am
Plenary Panel:
Advanced and New Capabilities Foreseen in Silicon Technology
Advanced and New Capabilities Foreseen in Silicon Technology
9:00 am – 11:50 am
Conference Sessions
12:00 pm – 1:00 pm
Luncheon Keynote Presentation:
Byron Anderson, Senior Vice President and General Manager, Electronic Products and Solutions Group, Agilent Technologies
Byron Anderson, Senior Vice President and General Manager, Electronic Products and Solutions Group, Agilent Technologies
12:30 pm – 6:00 pm
Exhibits Open
2:00 pm – 4:50 pm
Conference Sessions
4:00 pm – 5:15 pm
Electrical and Physical System Design Conference Panel:
Dealing with Deep Sub-Micron Design Issues for the 50-Million Transistor Chip
Dealing with Deep Sub-Micron Design Issues for the 50-Million Transistor Chip
4:00 pm – 5:15 pm
Leading-Edge Communications Design Systems Conference Panel:
Communications System Design Challenges at 40 Gbps
Communications System Design Challenges at 40 Gbps
4:45 pm – 6:00 pm
Exhibit Reception
Thursday, January 31, 2002
9:00 am – Noon
TecForums
