SC-TF1 Design Tradeoffs in Developing Personal Access Devices

SC-TF2 Advancements in Designing With FPGAs

HP-TF1 PCI-X: Designing Advanced I/O

HP-TF2 Improving Code Maintainability and Saving ROM Using Unified Macro Language

IP-TF1 USB 2.0 Function Controller Design and Verification

WB-TF1 High-Performance Logic Translation and Clock Distribution ICs Allow New Design Methodologies

SC-TF3 Platform-Based Design of SoC

SC-TF4 Tutorial on Design Closure

HP-TF3 Design and Testing of High-Speed Copper-Based Differential Board-to-Board Interconnection Solutions

HP-TF4 Functional Validation and Debug of InfiniBand Systems

IP-TF2 What Constitutes Star IP?

IP-TF3 Bridging RTL and C Standards

Wireless and Broadband Design Conference

WB-TF2 One-Day System Level Design Environment

SC-01 Techniques to Address Greater On-Chip Performance in SoC Applications

SC-02 Netlist Translation Without Vectors

HP-01 Using TDR and Frequency Domain Analysis to Ensure Signal Integrity in High-Speed Interconnects

HP-02 LVDS SERDES 660 Mbps Testing Uses JTAG, BIST, and Loopback

IP-01 An Intelligent Memory Approach Using Address and Data Port Processing

IP-02 Integrating LX4180: A VoIP ASSP Experience

WB-01 Performance Evaluation of Gbps Backplane Serial Links

WB-02 Top Ten Requirements for Service Discovery

SC-03 System-on-Chip Multi-Processor for Voice over IP

SC-04 Reconfigurable SoC Using an Embedded Module Array

HP-03 The Engineering Engine and InfiniBand Architecture at Speed

IP-03 IP Implementation in FPGAs

IP-04 Integration of a DDR Controller Into SoC ASIC

WB-03 Non-Linear Full Wave Time Domain Solutions Using FDTD–SPICE for High-Speed Digital and RF

WB-04 Architecture Determination in Optical Access Networks

SC-05 The Dynamics of SoC Design Methodologies and Application-Specific Platforms

SC-06A Design Verification: RTL Sign-Off and Design Intent Validation

SC-06B Hierarchical Design Methodology for Multi-Million Gate ASICs

HP-05 Advances in High-Speed Design in Dispersively Attenuating Environments, Such As Cables and Backplanes

HP-06 GTLP in Live Insertion Applications

IP-05 Application Extensions for DSP Core

IP-06A When Memories Forget: Soft Errors in Very Deep Sub-Micron Memories

IP-06B Development and Deployment of Star IP

WB-05 Overcoming Packaging Limitations in Wireless IC Designs

WB-06 Transactional Interactive Messaging: Utilizing a Dynamic Personal, Interactive Communications Portal

SC-07 The Programmable Logic Core: Enabling the Configurable System-on-Chip

SC-08 When All You Have Is Money: Verification Experience at a Start-Up

HP-07 Modeling Loss and Jitter in High-Speed Serial Interconnects

HP-08 Improved Method for Characterizing and Modeling Flex-Circuit–Based Connectors at 2.5 Gbps

IP-07 Clock Tuning Circuit for IP Core Integration in SoC

IP-08 Automated IP Core Integration Using Tool Command Language (TCL)

WB-07 Probing and Analyzing Communication Systems

WB-08 Bluetooth Compliance Validation at the RTL Design Stage

SC-09 FPSLIC for SoC: Micros with Muscles or FPGA with Brains?

SC-10 Verification Techniques for Processor-Based Communications SoCs

HP-09A Broadband Measurements in the Differential Mode: Accurate Determination of Dispersive Attenuation

HP-09B Rigorous Evaluation of Worst-Case Total Cross-Talk in the Time Domain Using Frequency Domain Scattering Parameters

HP-10 Signal Integrity Measurement and the Requirements Imposed by High-Speed Design

IP-09 An Asynchronous Buffer-and-Compare Circuit for Minimizing Glitches on Bit Vectors

IP-10 Analog HDLS in Design and Verification of Large ICs

WB-09 Design Analyses for Broadband, Non-Interfering, Multiple Access RF Communications Links from User Terminals to Comsat Hub in Two-Way VSAT Networks

WB-10 A Software Radio Approach for Broadband Wireless

HP-11 Using Silicon Technology to Extend the Useful Life of Backplane and Card Substrates at 3.125 Gbps and Beyond

HP-12 A 1.6 G-Bit/s/pin Multi-Level Parallel Interconnection

IP-11 8-Bit Microcontroller With Integrated Programmable Gain Amplifier in 10-Bit A/D Signal Path

IP-12 Internet Appliance Development Platform Using Intel StrongArm Processor and Xilinx PCI Core

Panel: The ASIC/FPGA Battle: Will a Hybrid Solution Win?

SC-11 Design of a Bluetooth Radio on a Chip

SC-12 Accelerating Inkjet Printer Design and Verification Through Flexible Hardware Emulation

HP-13A 2.5 Gbps Backplane Design, Simulation, and Measurement

HP-14 Designing and Verifying High-Speed Memory Buses

IP-13 Re-Usable IP Takes Center Stage in Rapid Prototyping and Verifying of SoC Design

IP-14 Real-World Requirements for an IP Re-Use System

WB-11 Open Switching Architectures

WB-12 Computing Without Computers

SC-13 AMBA Development Board Accelerates Peripheral Verification and Software Development

SC-14 Platform Approaches to Achieve SoC Designs in Six Months or Less

HP-15A Signal Integrity Considerations for 10 Gbit/s Transmission Over Backplane Systems

HP-15B Practical Characterization and Analysis of Lossy Transmission Line

HP-16 Design of a 3.2 GB/s Memory Sub-System for Play Station 2

IP-15 Verifying Virtual Components and VC–Based SoC Designs

IP-16 A Fundamental Design Problem: Finding the Right Design

WB-13 Signal Integrity: It Matters for Both Electrical and Optical Devices and Systems

WB-14 Vector-Based Graphical Modeling of Physical Layer (PHY) Functions in High-Performance Communications ICs

SC-15 Embedded Power Management in Mixed-Signal ASICs

SC-16 Automatic Bus Functional Model Test Bench Generation for PCI–Based Systems

HP-17 Demonstrator for Transmission Via Backplane in CMOS Technology at Data Rates of 2.5 gbps and Higher

HP-18 Source Synchronous Bus Design and Timing Analysis for High-Volume Manufacturable System Interconnect

IP-17 The Hardware Software Interface: The Weak Link?

IP-18 Web-Based Exchange of Complex DSP IP for Wireless SoC Applications

WB-15 IP Core–Based Design, High-Speed Processor Design and Multiplexing LAN Architectures Enabled by 3D Wafer Bonding Technologies

WB-16 IP–Centric Architecture for Optical Network Architecture

SC-17 Unified ASIC and FPGA Flows for Timing Convergence

SC-18 Design for Test in Mixed-Signal SoC: A Case Study

HP-19 Solution Space Analysis: Attacking the High-Speed Analysis Problem

HP-20 Layout Constraints for Signal Integrity on Digital Boards With Sub-Nanosecond Driver Edge Rates

IP-19 The Application of Trapezoidal Association of Transistors for Comparators and Sigma-Delta Modulators in a Pre-Diffused Digital CMOS Array

IP-20 Virtual Component Repository: Supplier Connect

WB-17 SOIS: Smart Optical Interconnection Systems

WB-18 Laser Micro-Machining for Optical Interconnection

SC-19 A Hierarchical Design Methodology for 50M Gate Designs

SC-20 Designing a Simple FPGA RISC CPU and System-on-Chip

WB-19 An Open Platform for Development of Network Processing Modules in Reprogrammable Hardware

WB-20 When Less Is More: Lowering Insertion Loss in High-Density Optical Connectors Is a Key Enabling Technology in Advanced Optical Systems Design

SC-TF5 TecForum: Functional Verification of Hardware and Software in Embedded Systems Designs: ASIC Verification

SC-TF6 TecForum: Internet-Aware Embedded Systems

HP-TF5 TecForum: High-Performance Bus Solutions Overview and Analysis of GTLP/BTL Backplane Design and Operation

IP-TF4 TecForum: Internet Intellectual Property Evaluation and SoC Verification: Accelerating Systems Design

WB-TF3 TecForum: A Next-Generation Digital Signal Processing Core Ideal for Communications Applications

WB-TF4 TecForum: Wireless Local Area Networks: Putting Technology Innovation Into Action